[RFC,net-next,0/2] Add Half Duplex support for ICSSG Driver

Message

MD Danish Anwar Aug. 30, 2023, 11:31 a.m. UTC

This series adds support for half duplex operation for ICSSG driver.

In order to support half-duplex operation at 10M and 100M link speeds, the
PHY collision detection signal (COL) should be routed to ICSSG
GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal
and apply the CSMA/CD algorithm applicable for half duplex operation. A DT
property, "ti,half-duplex-capable" is introduced for this purpose in the
first patch of the series. If board has PHY COL pin conencted to
PRGx_PRU1_GPIO10, this DT property can be added to eth node of ICSSG, MII
port to support half duplex operation at that port.

Second patch of the series configures driver to support half-duplex
operation if the DT property "ti,half-duplex-capable" is enabled.

This series depends on [1] which is posted as RFC.

[1] https://lore.kernel.org/all/[e-mail]/

Thanks and Regards,
Md Danish Anwar

MD Danish Anwar (2):
  dt-bindings: net: Add documentation for Half duplex support.
  net: ti: icssg-prueth: Add support for half duplex operation

 .../bindings/net/ti,icssg-prueth.yaml           |  7 +++++++
 drivers/net/ethernet/ti/icssg/icssg_config.c    | 14 ++++++++++++++
 drivers/net/ethernet/ti/icssg/icssg_prueth.c    | 17 +++++++++++++++--
 drivers/net/ethernet/ti/icssg/icssg_prueth.h    |  2 ++
 4 files changed, 38 insertions(+), 2 deletions(-)

Comments

Roger Quadros Sept. 7, 2023, 12:20 p.m. UTC | #1

On 30/08/2023 14:31, MD Danish Anwar wrote:
> This series adds support for half duplex operation for ICSSG driver.
> 
> In order to support half-duplex operation at 10M and 100M link speeds, the
> PHY collision detection signal (COL) should be routed to ICSSG
> GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal
> and apply the CSMA/CD algorithm applicable for half duplex operation. A DT
> property, "ti,half-duplex-capable" is introduced for this purpose in the
> first patch of the series. If board has PHY COL pin conencted to
> PRGx_PRU1_GPIO10, this DT property can be added to eth node of ICSSG, MII
> port to support half duplex operation at that port.
> 
> Second patch of the series configures driver to support half-duplex
> operation if the DT property "ti,half-duplex-capable" is enabled.
> 
> This series depends on [1] which is posted as RFC.
> 
> [1] https://lore.kernel.org/all/[e-mail]/
> 
> Thanks and Regards,
> Md Danish Anwar
> 
> MD Danish Anwar (2):
>   dt-bindings: net: Add documentation for Half duplex support.
>   net: ti: icssg-prueth: Add support for half duplex operation
> 
>  .../bindings/net/ti,icssg-prueth.yaml           |  7 +++++++
>  drivers/net/ethernet/ti/icssg/icssg_config.c    | 14 ++++++++++++++
>  drivers/net/ethernet/ti/icssg/icssg_prueth.c    | 17 +++++++++++++++--
>  drivers/net/ethernet/ti/icssg/icssg_prueth.h    |  2 ++
>  4 files changed, 38 insertions(+), 2 deletions(-)
> 

For this series:

Reviewed-by: Roger Quadros <[e-mail]>