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Fri, 5 Jul 2024 00:15:05 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Tariq Toukan Subject: [PATCH net-next 00/10] mlx5 misc patches 2023-07-05 Date: Fri, 5 Jul 2024 10:13:47 +0300 Message-ID: <20240705071357.1331313-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|CH2PR12MB4053:EE_ X-MS-Office365-Filtering-Correlation-Id: e2485a7c-3e58-4e64-caf0-08dc9cc23a42 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: Z82d2HhdRl0mof+HFCiw1oVh/+KIY6RVfWWOGmj7BMlXmJdRYWscG9s48CM/cgr2YbzG7uoYm8pzKh3Plfv89qgvll9woysH8Sj0B5Jgsm8vsvLHHNSxKNTq4y6fJnoEWqVNDdONOqBqnZ3a0SLkM7F9QsBzc/ZmjYraqzbkqTQ2PvS7RgM6LZkDA9DUgwrCblES0FdPaOq/yY8HrefkEF8YLCuqgtNUfDuz3nPJgBReyV/rSMSCPgrMqbR3ClROrvWbip5taw9WvBjxgH5M1VOP5cJfu5mt9oCAuwJQL+j0fLmzCKesmhl21+WyqBO6pO24bSDSaumEXea0pjGnn2VfPHj/Kt6iTz022TUxp2n7mcPdYgSY2gsRdNoAIy0FQUyo6C11mN40ZiSiDepNe3s+8HnciQoybpCwN74Mu4Szy60DCD3GRmcoKvOIKveTQttx2kcri/UOaoUXOLc3vJGaw/gPYhOupCJAhA/66vmpJhfO6mKxqWCD8d3umdRQby55RhJLeviLDaY7jGUL5h5Wq1MZVVT08qTaeX2rv8V68Z2C+Maute3wWMfuhbP3qunyHJZlpHJ3Cl328HWIKIrb7FLRz9tH9Xjbk/17b0FfvUU9jyQr1TjTVJu4++f3JX+NouZg9lnw5HXIdYYKAuw06iLJK4EUTe/ghFRYAgZ07NPFUD4OV+Lv6M55j5WaNwJaCqjUTMxBaP74AyO7xpvzgiv3wxf0YEyVVebN8tSA0o3032FcYC49IeyDUH7JAwLbHXAfBkYZNBV/vO0tYdOimMN/Hl8p1c+xcBdVxDY+QPgyCCQsqUrmQvdaoWbBgU4eltMa/1VUp+qnF6wQ3YH/XRM5ZksLr85a3m3MEj0f9hSk7soIKrNfUsQK2To4K2kgVql1VcBYTIiQoc5S3sDTuUjQ1BI6S+GC8A6t8f4DTIegMJOrhRku5fk9wIcIbqZBEEy5d0s5CzoOu97jw408LSNVop6C+Gculr0qUmjh5TqQO3SmfCHD811cUQNBYEvpy1VepVTCX2P9Hqw0+cZaRLXn1ggOHbhHpPFVOYN+xyUgJQ/Vsv3UwKGhrtQAElxlk9+6hK2lWvNFYiLoQg2KhIylFUdIui07N8dtAgw9bRBTtQE8zT2bLwkqdlqJzQ+HBMSXzt+9ObDqGfFEU0v77vvbQuuJd/kkQ/Lx7VnkyM2rqWEXlXkc0+GIeuH8egc3hHYrIjIQk+9IF6nJmLP2fcfvdTk8SYTp1SDNrF/KoY/vTPwzQ+gbvVn3WwKfenRAJNY278LXz0+Ep1gOzwN8kGFniHjODJX51SNR/my7eRCbPZpvOOYeakjiFE/E2dkD2gP1V1Temfj6Q5oTNjaiImGIN+ejQyhpdMhGP3kdD6X5RL5nOpmiM8+UmikH1Vu5qugOxnn2zPb87z+dSqgnwgw2xS4RP68LExRj36NwHU7w0h6Qcvps11Me4351 X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2024 07:15:19.3405 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2485a7c-3e58-4e64-caf0-08dc9cc23a42 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4053 X-Patchwork-Delegate: kuba@kernel.org Hi, This patchset contains features and small enhancements from the team to the mlx5 core and Eth drivers. In patches 1-4, Dan completes the max_num_eqs logic of the SF. Patches 5-7 by Rahul and Carolina add PTM (Precision Time Measurement) support to driver. PTM is a PCI extended capability introduced by PCI-SIG for providing an accurate read of the device clock offset without being impacted by asymmetric bus transfer rates. Patches 8-10 are misc fixes and cleanups. Series generated against: commit 390b14b5e9f6 ("dt-bindings: net: Define properties at top-level") Regards, Tariq Carolina Jubran (1): net/mlx5: Add support for enabling PTM PCI capability Cosmin Ratiu (1): net/mlx5e: CT: Initialize err to 0 to avoid warning Daniel Jurgens (4): net/mlx5: IFC updates for SF max IO EQs net/mlx5: Set sf_eq_usage for SF max EQs net/mlx5: Set default max eqs for SFs net/mlx5: Use set number of max EQs Dragos Tatulea (1): net/mlx5e: SHAMPO, Add missing aggregate counter Rahul Rameshbabu (2): net/mlx5: Add support for MTPTM and MTCTR registers net/mlx5: Implement PTM cross timestamping support Yevgeny Kliteynik (1): net/mlx5: DR, Remove definer functions from SW Steering API .../ethernet/mellanox/mlx5/core/en/tc_ct.c | 2 +- .../ethernet/mellanox/mlx5/core/en_stats.c | 2 + drivers/net/ethernet/mellanox/mlx5/core/eq.c | 7 +- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 3 + .../mellanox/mlx5/core/eswitch_offloads.c | 15 +++- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 1 + .../ethernet/mellanox/mlx5/core/lib/clock.c | 86 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/main.c | 6 ++ .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 12 +-- .../ethernet/mellanox/mlx5/core/sf/devlink.c | 12 +++ .../mellanox/mlx5/core/steering/dr_types.h | 5 ++ .../mellanox/mlx5/core/steering/mlx5dr.h | 5 -- include/linux/mlx5/device.h | 7 +- include/linux/mlx5/driver.h | 2 + include/linux/mlx5/mlx5_ifc.h | 47 +++++++++- 15 files changed, 193 insertions(+), 19 deletions(-)