| Message ID | 20240708080025.1593555-1-tariqt@nvidia.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | mlx5 misc patches 2023-07-08 | expand |
On Mon, Jul 08, 2024 at 11:00:15AM +0300, Tariq Toukan wrote: > Hi, > > This patchset contains features and small enhancements from the team to > the mlx5 core and Eth drivers. > > In patches 1-4, Dan completes the max_num_eqs logic of the SF. > > Patches 5-7 by Rahul and Carolina add PTM (Precision Time Measurement) > support to driver. PTM is a PCI extended capability introduced by > PCI-SIG for providing an accurate read of the device clock offset > without being impacted by asymmetric bus transfer rates. > > Patches 8-10 are misc fixes and cleanups. > > Series generated against: > commit 390b14b5e9f6 ("dt-bindings: net: Define properties at top-level") > > Regards, > Tariq > > V2: > - Fixed compilation issue on !X86 archs. Thanks, I have confirmed compilation on ARM and arm64. ...
On 08/07/2024 13:58, Simon Horman wrote: > On Mon, Jul 08, 2024 at 11:00:15AM +0300, Tariq Toukan wrote: >> Hi, >> >> This patchset contains features and small enhancements from the team to >> the mlx5 core and Eth drivers. >> >> In patches 1-4, Dan completes the max_num_eqs logic of the SF. >> >> Patches 5-7 by Rahul and Carolina add PTM (Precision Time Measurement) >> support to driver. PTM is a PCI extended capability introduced by >> PCI-SIG for providing an accurate read of the device clock offset >> without being impacted by asymmetric bus transfer rates. >> >> Patches 8-10 are misc fixes and cleanups. >> >> Series generated against: >> commit 390b14b5e9f6 ("dt-bindings: net: Define properties at top-level") >> >> Regards, >> Tariq >> >> V2: >> - Fixed compilation issue on !X86 archs. > > Thanks, I have confirmed compilation on ARM and arm64. > > ... > Great. Thank you.
Hello: This series was applied to netdev/net-next.git (main) by Jakub Kicinski <kuba@kernel.org>: On Mon, 8 Jul 2024 11:00:15 +0300 you wrote: > Hi, > > This patchset contains features and small enhancements from the team to > the mlx5 core and Eth drivers. > > In patches 1-4, Dan completes the max_num_eqs logic of the SF. > > [...] Here is the summary with links: - [net-next,V2,01/10] net/mlx5: IFC updates for SF max IO EQs (no matching commit) - [net-next,V2,02/10] net/mlx5: Set sf_eq_usage for SF max EQs (no matching commit) - [net-next,V2,03/10] net/mlx5: Set default max eqs for SFs (no matching commit) - [net-next,V2,04/10] net/mlx5: Use set number of max EQs (no matching commit) - [net-next,V2,05/10] net/mlx5: Add support for MTPTM and MTCTR registers (no matching commit) - [net-next,V2,06/10] net/mlx5: Add support for enabling PTM PCI capability (no matching commit) - [net-next,V2,07/10] net/mlx5: Implement PTM cross timestamping support (no matching commit) - [net-next,V2,08/10] net/mlx5: DR, Remove definer functions from SW Steering API https://git.kernel.org/netdev/net-next/c/e829a331ec28 - [net-next,V2,09/10] net/mlx5e: SHAMPO, Add missing aggregate counter https://git.kernel.org/netdev/net-next/c/7204730b3304 - [net-next,V2,10/10] net/mlx5e: CT: Initialize err to 0 to avoid warning https://git.kernel.org/netdev/net-next/c/f1ac0b7dcd49 You are awesome, thank you!
Hi, This patchset contains features and small enhancements from the team to the mlx5 core and Eth drivers. In patches 1-4, Dan completes the max_num_eqs logic of the SF. Patches 5-7 by Rahul and Carolina add PTM (Precision Time Measurement) support to driver. PTM is a PCI extended capability introduced by PCI-SIG for providing an accurate read of the device clock offset without being impacted by asymmetric bus transfer rates. Patches 8-10 are misc fixes and cleanups. Series generated against: commit 390b14b5e9f6 ("dt-bindings: net: Define properties at top-level") Regards, Tariq V2: - Fixed compilation issue on !X86 archs. Carolina Jubran (1): net/mlx5: Add support for enabling PTM PCI capability Cosmin Ratiu (1): net/mlx5e: CT: Initialize err to 0 to avoid warning Daniel Jurgens (4): net/mlx5: IFC updates for SF max IO EQs net/mlx5: Set sf_eq_usage for SF max EQs net/mlx5: Set default max eqs for SFs net/mlx5: Use set number of max EQs Dragos Tatulea (1): net/mlx5e: SHAMPO, Add missing aggregate counter Rahul Rameshbabu (2): net/mlx5: Add support for MTPTM and MTCTR registers net/mlx5: Implement PTM cross timestamping support Yevgeny Kliteynik (1): net/mlx5: DR, Remove definer functions from SW Steering API .../ethernet/mellanox/mlx5/core/en/tc_ct.c | 2 +- .../ethernet/mellanox/mlx5/core/en_stats.c | 2 + drivers/net/ethernet/mellanox/mlx5/core/eq.c | 7 +- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 3 + .../mellanox/mlx5/core/eswitch_offloads.c | 15 +++- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 1 + .../ethernet/mellanox/mlx5/core/lib/clock.c | 88 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/main.c | 6 ++ .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 12 +-- .../ethernet/mellanox/mlx5/core/sf/devlink.c | 12 +++ .../mellanox/mlx5/core/steering/dr_types.h | 5 ++ .../mellanox/mlx5/core/steering/mlx5dr.h | 5 -- include/linux/mlx5/device.h | 7 +- include/linux/mlx5/driver.h | 2 + include/linux/mlx5/mlx5_ifc.h | 47 +++++++++- 15 files changed, 195 insertions(+), 19 deletions(-)