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Mon, 8 Jul 2024 01:01:28 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Tariq Toukan Subject: [PATCH net-next V2 00/10] mlx5 misc patches 2023-07-08 Date: Mon, 8 Jul 2024 11:00:15 +0300 Message-ID: <20240708080025.1593555-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002320:EE_|PH0PR12MB8175:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ef2c928-5ab1-42ed-35b1-08dc9f24337b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: s2/8b+LnTvFMUki4NGj6BxC4PxOPUDRW0UpTVjxRcLJzn8GjSWxfkF9Rwx4i9R5wTYy3x6GwZErcQ3uqRmRJZOlFZnQFKBIZFeKiQ1akWRM3uk7F3s7+Gnf+Y8EvGvmPjaBgIK5iebDxV+3Ka5cMnm1JZCVF+yzmmHrRaEruJ8KzfhGiimYWoQkdgKe1kHCEc46d4OWYm4i0sXHLFz61ht6v/dIuDFov4vvHCUemZ/re8pQ6dYhnGkA8EPDYttH/jBYc8+6dFj7cl+SlKCkTKkaF/SULs9UMzkqCDFGO1I1WO6cTF4pc6ZdoP/sYmhi3+9P+4NDCzy4PBqxAfSIFw4dXRLe/HyASexjqf9F5XeRYxK3w7HI0PHf7kNUSHkZs83T5WqRDjLu/Bhmx7W5dKIr6/178WK47AGgoMd4G9flO/4pNQx61zblbivqnKVidThKfO5F8WntmV/yZcOJWnwLSt7ZryBPjxdfFdYKTMtEGL7Dm6lHnQ/l3L+8zBP7Y68Mircc130u0WpJ2RnY6GZhhh0aDucNyT0biHPu6njw+RsslWwvarHsTwE3ruA+l2T/+JipvAOXeAGY0FvGZQVMo77aiGJulyVSDXCjQ8z76VZN4RrQDP2xJFJCdVKxTSog5yfU/RVNiV6UWbUJ0uBM+tZCbYT2TOMDmWr37vPPPLUtKVvS7F7NpzUHNJ0Vm+XdqH+kJKBDp/x1xCA642oe5uBKcRRYpY8nJmC03MRGTrqej+kxziaH5+TLLnjeyzBJk1cL/NX01eZeMij/8cHBXB6JYinW8rNWR0hm0JOUVs+7EeInCbrAL9Dsge3mO0sw4TbGWkk9zCYTRRDWBgzYIkRESMH6lJrHSxzfQD7K5f6vPKrqH3djX0R4uI65mh4HGrQetFNPj6Chbg9SOT4epoP7oue54j9q0sEBnscfc9xDGDxgNLtVBq5A+nzX5VU6yR4osI/1+KsjKrPuqwgsWX4Itwer7wFnha5VGt6aqwv0n6IV79w65S6SRAQbsxwbptrA35ZdH3XT6wVfs7Eoua1DrTQzoeLmC1xlam95i2vTpCkGa3yYL2CcxPTHWquKX+vxA48r75cI9pR4mfgi0vO53VvA4U0bdIFwhEasZHsQ9BxxbyBDdfYjSWPW2HXqqZbGt6YU1pbqHgWfZsyA5FWCxxmUpJHkLQ0qk9NrqxS8cR85/7/a90YTCMOLB8b3+v+rYVcDG/Nlx/WxKgvfyi7HIQN4uV5KKaZcOvGw67jFMhnkjqIk/ykT1U+WJjMpV9VsF/ezbv8lNNaAtbvbvaHmB9xiLcYiDIQeYGIV2bk8ffmg4R24BlSwfnoHPAOeD1U5o3Lu7X6ZpgouGhEYseLhZo/S9jZIQ30abjY+dTG5kLe4lYmWsVGcsIbshy04J0A7wip2OxpRw9/vbHIvaixGshjR6ECknbEQrHa58Oj2QJtsaupe2803ro0S1 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 08:01:41.0807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ef2c928-5ab1-42ed-35b1-08dc9f24337b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002320.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8175 X-Patchwork-Delegate: kuba@kernel.org Hi, This patchset contains features and small enhancements from the team to the mlx5 core and Eth drivers. In patches 1-4, Dan completes the max_num_eqs logic of the SF. Patches 5-7 by Rahul and Carolina add PTM (Precision Time Measurement) support to driver. PTM is a PCI extended capability introduced by PCI-SIG for providing an accurate read of the device clock offset without being impacted by asymmetric bus transfer rates. Patches 8-10 are misc fixes and cleanups. Series generated against: commit 390b14b5e9f6 ("dt-bindings: net: Define properties at top-level") Regards, Tariq V2: - Fixed compilation issue on !X86 archs. Carolina Jubran (1): net/mlx5: Add support for enabling PTM PCI capability Cosmin Ratiu (1): net/mlx5e: CT: Initialize err to 0 to avoid warning Daniel Jurgens (4): net/mlx5: IFC updates for SF max IO EQs net/mlx5: Set sf_eq_usage for SF max EQs net/mlx5: Set default max eqs for SFs net/mlx5: Use set number of max EQs Dragos Tatulea (1): net/mlx5e: SHAMPO, Add missing aggregate counter Rahul Rameshbabu (2): net/mlx5: Add support for MTPTM and MTCTR registers net/mlx5: Implement PTM cross timestamping support Yevgeny Kliteynik (1): net/mlx5: DR, Remove definer functions from SW Steering API .../ethernet/mellanox/mlx5/core/en/tc_ct.c | 2 +- .../ethernet/mellanox/mlx5/core/en_stats.c | 2 + drivers/net/ethernet/mellanox/mlx5/core/eq.c | 7 +- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 3 + .../mellanox/mlx5/core/eswitch_offloads.c | 15 +++- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 1 + .../ethernet/mellanox/mlx5/core/lib/clock.c | 88 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/main.c | 6 ++ .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 12 +-- .../ethernet/mellanox/mlx5/core/sf/devlink.c | 12 +++ .../mellanox/mlx5/core/steering/dr_types.h | 5 ++ .../mellanox/mlx5/core/steering/mlx5dr.h | 5 -- include/linux/mlx5/device.h | 7 +- include/linux/mlx5/driver.h | 2 + include/linux/mlx5/mlx5_ifc.h | 47 +++++++++- 15 files changed, 195 insertions(+), 19 deletions(-)