Message ID | 0105ba8db974bca74846d605b18dcf948a7ab3d9.1678201958.git.daniel@makrotopia.org (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | net: ethernet: mtk_eth_soc: various enhancements | expand |
> Gesendet: Dienstag, 07. März 2023 um 16:53 Uhr > Von: "Daniel Golle" <daniel@makrotopia.org> > > Reset the internal PCS state machine when changing interface mode. > This prevents confusing the state machine when changing interface > modes, e.g. from SGMII to 2500Base-X or vice-versa. > > Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> > Tested-by: Bjørn Mork <bjorn@mork.no> > Signed-off-by: Daniel Golle <daniel@makrotopia.org> Hi, have tested Parts 1-12 this on bananapi-r3 (mt7986) with 1G Fiber SFP (no 2g5 available yet) on gmac1 and lan4 (mt7531 p5) Tested-by: Frank Wunderlich <frank-w@public-files.de> Thx Daniel for working on SFP support :) regards Frank
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 7014c02ba2d4..142def8629c8 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -548,6 +548,10 @@ #define SGMII_SEND_AN_ERROR_EN BIT(11) #define SGMII_IF_MODE_MASK GENMASK(5, 1) +/* Register to reset SGMII design */ +#define SGMII_RESERVED_0 0x34 +#define SGMII_SW_RESET BIT(0) + /* Register to set SGMII speed, ANA RG_ Control Signals III*/ #define SGMSYS_ANA_RG_CS3 0x2028 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c index d7ffaaeaf9ab..d7e7352041a4 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -88,6 +88,10 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode, regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD, SGMII_PHYA_PWD); + /* Reset SGMII PCS state */ + regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0, + SGMII_SW_RESET, SGMII_SW_RESET); + if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP) regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, SGMII_PN_SWAP_MASK,