@@ -429,7 +429,6 @@
#define RCANFD_C_RPGACC(r) (0x1900 + (0x04 * (r)))
/* R-Car V3U Classical and CAN FD mode specific register map */
-#define RCANFD_V3U_DCFG(m) (0x1400 + (0x20 * (m)))
#define RCANFD_V3U_FDCFG(m) (0x1404 + (0x20 * (m)))
#define RCANFD_V3U_GAFL_OFFSET (0x1800)
@@ -437,7 +436,7 @@
/* CAN FD mode specific register map */
/* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
-#define RCANFD_F_DCFG(m) (0x0500 + (0x20 * (m)))
+#define RCANFD_F_DCFG(gpriv, m) (reg_v3u(gpriv, 0x1400, 0x0500) + (0x20 * (m)))
#define RCANFD_F_CFDCFG(m) (0x0504 + (0x20 * (m)))
#define RCANFD_F_CFDCTR(m) (0x0508 + (0x20 * (m)))
#define RCANFD_F_CFDSTS(m) (0x050c + (0x20 * (m)))
@@ -1346,10 +1345,7 @@ static void rcar_canfd_set_bittiming(struct net_device *dev)
cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
- if (is_v3u(gpriv))
- rcar_canfd_write(priv->base, RCANFD_V3U_DCFG(ch), cfg);
- else
- rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
+ rcar_canfd_write(priv->base, RCANFD_F_DCFG(gpriv, ch), cfg);
netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
brp, sjw, tseg1, tseg2);
} else {
Abstract the different addresses for the Channel n Data Bitrate Configuration Register (DCFG) in the definition of the register macro, like is already done for other register definitions, to simplify code accessing this register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- drivers/net/can/rcar/rcar_canfd.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)