From patchwork Tue Aug 31 22:28:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Chan X-Patchwork-Id: 12467861 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY, MIME_NO_TEXT,SPF_HELO_NONE,SPF_PASS,T_TVD_MIME_NO_HEADERS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81902C432BE for ; Tue, 31 Aug 2021 22:29:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5A34661074 for ; Tue, 31 Aug 2021 22:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240854AbhHaW3x (ORCPT ); Tue, 31 Aug 2021 18:29:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240709AbhHaW3v (ORCPT ); Tue, 31 Aug 2021 18:29:51 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03FE9C061575 for ; Tue, 31 Aug 2021 15:28:56 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id v123so470414pfb.11 for ; Tue, 31 Aug 2021 15:28:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id; bh=MnvGxc/CR7fCGHnBUg5qo1ALqMcu4PDho01xtGLuzJ0=; b=ZZON06ScwmSBRIS/m16oWSF8ep8mWvFG7sMCD9GKcGMWjvcAqUFyG70maRoCSU4ff6 Oe+gLaDm28GXtCpL6/mOlgLgBZ3pyOU0S98B+Fsi0y/BxBtFxX+QRabX+YDd/RTQnVK8 UaykOCdPIxI/UrmlaKjXHO2LsC8D8+T/wlu7w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=MnvGxc/CR7fCGHnBUg5qo1ALqMcu4PDho01xtGLuzJ0=; b=LD2UVqdSA0Bl5/5bTLpAW3oNAVetUSWb+Lc3xWmAzw9AZr7SLI3i5Hx6h1mGJJldYJ I1BL2cgcwOlipbuU5AgGS5aQVKEs0krLWwNNJyIwXlZp6oF+VaXFmL2Ph1qJxIJ37sWc pDpsrZEQ3sIURJw5VFL4wzYXWT33pBo9flgzhvqmGVMwToSHHU0M7j8oXFqI0dZ4S/XT 6pyXjyS2HYBR+AUBKGOglt9LoELoinApNBZ9W4v5c402GUZui94YVj4JiIcxnD3iP2aE KlGOInKSmPFX9HxmoVbR24Yqin3ocSdXKxAUtVdh3gRTAxuTPIKAMZy22NOhSoV2zqWs sGUA== X-Gm-Message-State: AOAM532VjvfwEXRhc23Bi86N5KAkIHHZNM0vCX7PJTG5a0gf3vNtERQN /Jg2NUZ9o/0q+j/mowE7S7GpTUH1gOoQOA== X-Google-Smtp-Source: ABdhPJwEaepSezdFBd/6I60sv5zzl5OiroOMHToa8dGFg7PV8a9ckU/Yi4ushxkz/yQK3Zw1/5Hs9w== X-Received: by 2002:a63:f501:: with SMTP id w1mr28822203pgh.57.1630448934858; Tue, 31 Aug 2021 15:28:54 -0700 (PDT) Received: from localhost.swdvt.lab.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id w2sm3707617pjq.5.2021.08.31.15.28.53 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Aug 2021 15:28:54 -0700 (PDT) From: Michael Chan To: davem@davemloft.net Cc: netdev@vger.kernel.org, kuba@kernel.org, edwin.peer@broadcom.com, gospo@broadcom.com Subject: [PATCH net-next] bnxt_en: Fix 64-bit doorbell operation on 32-bit kernels Date: Tue, 31 Aug 2021 18:28:45 -0400 Message-Id: <1630448925-6740-1-git-send-email-michael.chan@broadcom.com> X-Mailer: git-send-email 1.8.3.1 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The driver requires 64-bit doorbell writes to be atomic on 32-bit architectures. So we redefined writeq as a new macro with spinlock protection on 32-bit architectures. This created a new warning when we added a new file in a recent patchset. writeq is defined on many 32-bit architectures to do the memory write non-atomically and it generated a new macro redefined warning. This warning was fixed incorrectly in the recent patch. Fix this properly by adding a new bnxt_writeq() function that will do the non-atomic write under spinlock on 32-bit systems. All callers in the driver will now call bnxt_writeq() instead. Reported-by: kernel test robot Fixes: f9ff578251dc ("bnxt_en: introduce new firmware message API based on DMA pools") Reviewed-by: Edwin Peer Signed-off-by: Michael Chan --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 14 +++++----- drivers/net/ethernet/broadcom/bnxt/bnxt.h | 33 ++++++++++++++--------- 2 files changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index 627f85ee3922..5b145077d21a 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -305,13 +305,15 @@ static bool bnxt_vf_pciid(enum board_idx idx) writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell) #define BNXT_DB_NQ_P5(db, idx) \ - writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell) + bnxt_writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), \ + (db)->doorbell) #define BNXT_DB_CQ_ARM(db, idx) \ writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell) #define BNXT_DB_NQ_ARM_P5(db, idx) \ - writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell) + bnxt_writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), \ + (db)->doorbell) static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) { @@ -332,8 +334,8 @@ static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) { if (bp->flags & BNXT_FLAG_CHIP_P5) - writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), - db->doorbell); + bnxt_writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx), + db->doorbell); else BNXT_DB_CQ(db, idx); } @@ -2638,8 +2640,8 @@ static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi, if (cpr2 && cpr2->had_work_done) { db = &cpr2->cp_db; - writeq(db->db_key64 | dbr_type | - RING_CMP(cpr2->cp_raw_cons), db->doorbell); + bnxt_writeq(db->db_key64 | dbr_type | + RING_CMP(cpr2->cp_raw_cons), db->doorbell); cpr2->had_work_done = 0; } } diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h index a8212dcdad5f..e69d4a1d0c63 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h @@ -1981,7 +1981,7 @@ struct bnxt { struct mutex sriov_lock; #endif -#ifndef writeq +#if BITS_PER_LONG == 32 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */ spinlock_t db_lock; #endif @@ -2110,24 +2110,33 @@ static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); } -#ifndef writeq -#define writeq(val64, db) \ -do { \ - spin_lock(&bp->db_lock); \ - writel((val64) & 0xffffffff, db); \ - writel((val64) >> 32, (db) + 4); \ - spin_unlock(&bp->db_lock); \ -} while (0) +static inline void bnxt_writeq(u64 val, volatile void __iomem *addr) +{ +#if BITS_PER_LONG == 32 + spin_lock(&bp->db_lock); + writel(val & 0xffffffff, addr); + writel(val >> 32, addr + 4); + spin_unlock(&bp->db_lock); +#else + writeq(val, addr); +#endif +} -#define writeq_relaxed writeq +static inline void bnxt_writeq_relaxed(u64 val, volatile void __iomem *addr) +{ +#if BITS_PER_LONG == 32 + bnxt_writeq(val, addr); +#else + writeq_relaxed(val, addr); #endif +} /* For TX and RX ring doorbells with no ordering guarantee*/ static inline void bnxt_db_write_relaxed(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) { if (bp->flags & BNXT_FLAG_CHIP_P5) { - writeq_relaxed(db->db_key64 | idx, db->doorbell); + bnxt_writeq_relaxed(db->db_key64 | idx, db->doorbell); } else { u32 db_val = db->db_key32 | idx; @@ -2142,7 +2151,7 @@ static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) { if (bp->flags & BNXT_FLAG_CHIP_P5) { - writeq(db->db_key64 | idx, db->doorbell); + bnxt_writeq(db->db_key64 | idx, db->doorbell); } else { u32 db_val = db->db_key32 | idx;