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Mon, 7 Aug 2023 00:52:19 -0500 From: Radhey Shyam Pandey To: , , , , , , , , , CC: , , , , , , Radhey Shyam Pandey Subject: [PATCH net-next v5 03/10] dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client Date: Mon, 7 Aug 2023 11:21:42 +0530 Message-ID: <1691387509-2113129-4-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|MW3PR12MB4427:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ade9099-b0c3-4984-f380-08db970a847f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2WaHYWHHwZHk/spKTgxO+c0r/0CWgqF2HJflRstA7riA4KXjBXNXmxfI71eD+VAA2yPCxCxVvfA4FoCvliQvjpQO30/zTqZhluH98beJOtBQLGMgWF6RmQ7nw3p0nM/s0LJ2ILT2/880hUM6cyyV6nyBZXNjq+Ne5ovHv7vS8ZUE1ga1Ryh56S2H66gwqnCDKpV7cIRIsOBKIspK8e99Epjn3CEQ01Vnmgt1ttNl/U7qCztz9B5/b3FIUGkXmqhYkaOkSvmMbnDd112kmHWwl3tVfUgKu4CrwU/UNI/rFXpUtW3Tn9R281xIBQSI119HjSSHZIp8lPfaZalxz87lIm7lkTK6x/Kv1GSD7Gfx7W2TiK3+csglv5CSvl4s5oiJdh+nsdY+uyTuu84SSEroZabPOjRAU+jxqsX+hRllPrIndASyg58IZHU88SSdZDp2WiuawWKAZiqjvM8hk/eJeDQ7n+rg3u4lzwLzQj6/YHdvTn3j2wwfulcRlncW9JVRtgcxL1i34a+GJJ8nt02I320mybFNkaDx5BCy6vD7D28S0aHYvFV17H1Hvp0df1aGHkPThPhxHYinKO5xiV9BpM84D36xz0hvFV2NPQV1dHPmMJy4zD0xUv8kDfPfYMwalcyzQfTAxp9UkFfMNNeeXOQt7kV/8GbkE7IYuMz9QvR0YrFJ9BiKDS99Xi3WggBn/ViTlW1LF94YGGTYh9IvLr7JqpYGmLF+w5M4OmkmbvZRtJiPokLDLvf8GeQNfoYVMa26/T6SplI1lDepJkTsmtrI60u3NgVYqsEwID8RJyBuAhBoEWNtvO59cf6eHuWx X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(396003)(346002)(376002)(451199021)(186006)(82310400008)(1800799003)(40470700004)(46966006)(36840700001)(40480700001)(336012)(40460700003)(2616005)(36756003)(966005)(4326008)(316002)(86362001)(81166007)(478600001)(921005)(82740400003)(54906003)(110136005)(356005)(70206006)(70586007)(6666004)(41300700001)(26005)(426003)(8676002)(8936002)(47076005)(36860700001)(2906002)(7416002)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2023 05:52:43.0252 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ade9099-b0c3-4984-f380-08db970a847f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4427 X-Spam-Status: No, score=-0.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Read DT property to check if AXI DMA is connected to streaming IP i.e axiethernet. If connected i.e xlnx,axistream-connected property is present in the dma node then pass AXI4-Stream control words to dma client using metadata_ops dmaengine API. If not connected then driver won't support metadata_ops dmaengine API and continue to support all legacy usecases. Signed-off-by: Radhey Shyam Pandey --- Changes for v5: - New patch in this series. Just a note that dmaengine series was earlier sent as separate series[1] and now it's merged with axiethernet series[2]. [1]: https://lore.kernel.org/all/20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com [2]: https://lore.kernel.org/all/20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com - Modified the commit description to describe driver behavior when xlnx,axistream-connected is not present. - Switch to amd.com email address. --- drivers/dma/xilinx/xilinx_dma.c | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index ac09f0e5f58d..d526e472b905 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -493,6 +493,7 @@ struct xilinx_dma_config { * @s2mm_chan_id: DMA s2mm channel identifier * @mm2s_chan_id: DMA mm2s channel identifier * @max_buffer_len: Max buffer length + * @has_axistream_connected: AXI DMA connected to AXI Stream IP */ struct xilinx_dma_device { void __iomem *regs; @@ -511,6 +512,7 @@ struct xilinx_dma_device { u32 s2mm_chan_id; u32 mm2s_chan_id; u32 max_buffer_len; + bool has_axistream_connected; }; /* Macros */ @@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, } } +/** + * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length + * @tx: async transaction descriptor + * @payload_len: metadata payload length + * @max_len: metadata max length + * Return: The app field pointer. + */ +static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, + size_t *payload_len, size_t *max_len) +{ + struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); + struct xilinx_axidma_tx_segment *seg; + + *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; + seg = list_first_entry(&desc->segments, + struct xilinx_axidma_tx_segment, node); + return seg->hw.app; +} + +static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { + .get_ptr = xilinx_dma_get_metadata_ptr, +}; + /* ----------------------------------------------------------------------------- * Descriptors and segments alloc and free */ @@ -2221,6 +2246,9 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( segment->hw.control |= XILINX_DMA_BD_EOP; } + if (chan->xdev->has_axistream_connected) + desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; + return &desc->async_tx; error: @@ -3067,6 +3095,11 @@ static int xilinx_dma_probe(struct platform_device *pdev) } } + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { + xdev->has_axistream_connected = + of_property_read_bool(node, "xlnx,axistream-connected"); + } + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { err = of_property_read_u32(node, "xlnx,num-fstores", &num_frames); @@ -3092,6 +3125,10 @@ static int xilinx_dma_probe(struct platform_device *pdev) else xdev->ext_addr = false; + /* Set metadata mode */ + if (xdev->has_axistream_connected) + xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; + /* Set the dma mask bits */ err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); if (err < 0) {