| Message ID | 1c7efdf5d384ea7af3c0209723e40b2ee0f956bf.1700239272.git.lorenzo@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 31c54867fdea452023cc5faba939a6afec1b9d7e |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net-next] net: ethernet: mtk_wed: add support for devices with more than 4GB of dram | expand |
Hello: This patch was applied to netdev/net-next.git (main) by Jakub Kicinski <kuba@kernel.org>: On Fri, 17 Nov 2023 17:42:59 +0100 you wrote: > Introduce WED offloading support for boards with more than 4GB of > memory. > > Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com> > Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > > [...] Here is the summary with links: - [net-next] net: ethernet: mtk_wed: add support for devices with more than 4GB of dram https://git.kernel.org/netdev/net-next/c/31c54867fdea You are awesome, thank you!
Hi! On Fri, Nov 17, 2023 at 05:42:59PM +0100, Lorenzo Bianconi wrote: > Introduce WED offloading support for boards with more than 4GB of > memory. > > [...] > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c > index 3cf6589cfdac..a6e91573f8da 100644 > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c > @@ -1159,15 +1159,18 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) > phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); > > for (i = 0; i < cnt; i++) { > + dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE; > struct mtk_tx_dma_v2 *txd; > > txd = eth->scratch_ring + i * soc->txrx.txd_size; > - txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; > + txd->txd1 = addr; > if (i < cnt - 1) > txd->txd2 = eth->phy_scratch_ring + > (i + 1) * soc->txrx.txd_size; > > txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); > + if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) > + txd->txd3 |= TX_DMA_PREP_ADDR64(addr); > txd->txd4 = 0; > if (mtk_is_netsys_v2_or_greater(eth)) { > txd->txd5 = 0; The above part of the patch should also be applied to 'net' tree as fix for commit 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988"). It should have probably been a separate commit in first place, but it is how it is now and I'm glad that it fixes the remaining issues on devices devices with 4 GiB of RAM or more (and hence exceeding the 32-bit addressing range given that DRAM starts at 0x40000000; the commit message here states that only boards with more than 4 GiB are affected, but in reality it's boards with more then 3 GiB because of the DRAM start offset). Reported-by: Elad Yifee <eladwf@gmail.com>
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 3cf6589cfdac..a6e91573f8da 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1159,15 +1159,18 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); for (i = 0; i < cnt; i++) { + dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE; struct mtk_tx_dma_v2 *txd; txd = eth->scratch_ring + i * soc->txrx.txd_size; - txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; + txd->txd1 = addr; if (i < cnt - 1) txd->txd2 = eth->phy_scratch_ring + (i + 1) * soc->txrx.txd_size; txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); + if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) + txd->txd3 |= TX_DMA_PREP_ADDR64(addr); txd->txd4 = 0; if (mtk_is_netsys_v2_or_greater(eth)) { txd->txd5 = 0; diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c index 2ac35543fcfb..c895e265ae0e 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed.c +++ b/drivers/net/ethernet/mediatek/mtk_wed.c @@ -691,10 +691,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev) for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) { struct mtk_wdma_desc *desc = desc_ptr; + u32 ctrl; desc->buf0 = cpu_to_le32(buf_phys); if (!mtk_wed_is_v3_or_greater(dev->hw)) { - u32 txd_size, ctrl; + u32 txd_size; txd_size = dev->wlan.init_buf(buf, buf_phys, token++); @@ -708,11 +709,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev) ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 | FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2, MTK_WED_BUF_SIZE - txd_size); - desc->ctrl = cpu_to_le32(ctrl); desc->info = 0; } else { - desc->ctrl = cpu_to_le32(token << 16); + ctrl = token << 16 | TX_DMA_PREP_ADDR64(buf_phys); } + desc->ctrl = cpu_to_le32(ctrl); desc_ptr += desc_size; buf += MTK_WED_BUF_SIZE; @@ -811,6 +812,7 @@ mtk_wed_hwrro_buffer_alloc(struct mtk_wed_device *dev) buf_phys = page_phys; for (s = 0; s < MTK_WED_RX_BUF_PER_PAGE; s++) { desc->buf0 = cpu_to_le32(buf_phys); + desc->token = cpu_to_le32(RX_DMA_PREP_ADDR64(buf_phys)); buf_phys += MTK_WED_PAGE_BUF_SIZE; desc++; } diff --git a/drivers/net/ethernet/mediatek/mtk_wed_wo.c b/drivers/net/ethernet/mediatek/mtk_wed_wo.c index 3bd51a3d6650..7ffbd4fca881 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed_wo.c +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.c @@ -142,7 +142,8 @@ mtk_wed_wo_queue_refill(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q, dma_addr_t addr; void *buf; - buf = page_frag_alloc(&q->cache, q->buf_size, GFP_ATOMIC); + buf = page_frag_alloc(&q->cache, q->buf_size, + GFP_ATOMIC | GFP_DMA32); if (!buf) break;