From patchwork Mon Nov 9 12:09:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 11891383 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82711C4741F for ; Mon, 9 Nov 2020 12:10:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25EED20789 for ; Mon, 9 Nov 2020 12:10:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="LM1cKjAr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729566AbgKIMKG (ORCPT ); Mon, 9 Nov 2020 07:10:06 -0500 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:36332 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726410AbgKIMKG (ORCPT ); Mon, 9 Nov 2020 07:10:06 -0500 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0A9C0co5011687; Mon, 9 Nov 2020 04:10:00 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=3tYZGR1MS7+kZNb/qCfjCM7Z17EeuezMBTJq3OvzK2w=; b=LM1cKjArUuaRiJHWsUVPLqWXiBeekmTygKKxUA3XwVjkx3j5RLYxAYwLHItJK2lfVdV/ v0O51U8pgquCq2o31cEe/FnjsuCfSRiYiAMuwGWzidbCBD9ujLzwIhnAbMucn9nu/l/X jtFv0yrvFjC2Fz8Whc61altJYgHfyY3ct8UoMr+MgeS1zr8BXBC7jOFvI57JIAzOJXJx dVomYGUhEObm9A/eri0SHJWbiqQI2mUeWqp87Pzvphetv8UjfCx8RxEVx6KUqvPuh+R3 t7EowZXQssoA7fu9XO9d27oIhFXyNFwFN+3TzSytAAr3E9HdS56vkupMjy9EuSQ8FZKL fw== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 34nstttwqp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 09 Nov 2020 04:10:00 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 9 Nov 2020 04:09:59 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 9 Nov 2020 04:09:59 -0800 Received: from hyd1schalla-dt.marvell.com (hyd1schalla-dt.marvell.com [10.29.8.39]) by maili.marvell.com (Postfix) with ESMTP id 0F3143F7040; Mon, 9 Nov 2020 04:09:55 -0800 (PST) From: Srujana Challa To: , CC: , , , , , , , , Srujana Challa Subject: [PATCH v9,net-next,01/12] octeontx2-pf: move lmt flush to include/linux/soc Date: Mon, 9 Nov 2020 17:39:13 +0530 Message-ID: <20201109120924.358-2-schalla@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201109120924.358-1-schalla@marvell.com> References: <20201109120924.358-1-schalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312,18.0.737 definitions=2020-11-09_02:2020-11-05,2020-11-09 signatures=0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org On OcteonTX2 platform CPT instruction enqueue and NIX packet send are only possible via LMTST operations which uses LDEOR instruction. This patch moves lmt flush function from OcteonTX2 nic driver to include/linux/soc since it will be used by OcteonTX2 CPT and NIC driver for LMTST. Signed-off-by: Suheil Chandran Signed-off-by: Srujana Challa --- MAINTAINERS | 2 ++ .../marvell/octeontx2/nic/otx2_common.h | 13 +-------- include/linux/soc/marvell/octeontx2/asm.h | 29 +++++++++++++++++++ 3 files changed, 32 insertions(+), 12 deletions(-) create mode 100644 include/linux/soc/marvell/octeontx2/asm.h diff --git a/MAINTAINERS b/MAINTAINERS index 2a0fde12b650..a3452419ef8d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10466,6 +10466,7 @@ M: Srujana Challa L: linux-crypto@vger.kernel.org S: Maintained F: drivers/crypto/marvell/ +F: include/linux/soc/marvell/octeontx2/ MARVELL GIGABIT ETHERNET DRIVERS (skge/sky2) M: Mirko Lindner @@ -10538,6 +10539,7 @@ M: hariprasad L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/marvell/octeontx2/nic/ +F: include/linux/soc/marvell/octeontx2/ MARVELL OCTEONTX2 RVU ADMIN FUNCTION DRIVER M: Sunil Goutham diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 386cb08497e4..5b7517f13fb5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "otx2_reg.h" @@ -423,21 +424,9 @@ static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) return result; } -static inline u64 otx2_lmt_flush(uint64_t addr) -{ - u64 result = 0; - - __asm__ volatile(".cpu generic+lse\n" - "ldeor xzr,%x[rf],[%[rs]]" - : [rf]"=r"(result) - : [rs]"r"(addr)); - return result; -} - #else #define otx2_write128(lo, hi, addr) #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) -#define otx2_lmt_flush(addr) ({ 0; }) #endif /* Alloc pointer from pool/aura */ diff --git a/include/linux/soc/marvell/octeontx2/asm.h b/include/linux/soc/marvell/octeontx2/asm.h new file mode 100644 index 000000000000..ae2279fe830a --- /dev/null +++ b/include/linux/soc/marvell/octeontx2/asm.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * Copyright (C) 2020 Marvell. + */ + +#ifndef __SOC_OTX2_ASM_H +#define __SOC_OTX2_ASM_H + +#if defined(CONFIG_ARM64) +/* + * otx2_lmt_flush is used for LMT store operation. + * On octeontx2 platform CPT instruction enqueue and + * NIX packet send are only possible via LMTST + * operations and it uses LDEOR instruction targeting + * the coprocessor address. + */ +#define otx2_lmt_flush(ioaddr) \ +({ \ + u64 result = 0; \ + __asm__ volatile(".cpu generic+lse\n" \ + "ldeor xzr, %x[rf], [%[rs]]" \ + : [rf]"=r" (result) \ + : [rs]"r" (ioaddr)); \ + (result); \ +}) +#else +#define otx2_lmt_flush(ioaddr) ({ 0; }) +#endif + +#endif /* __SOC_OTX2_ASM_H */