| Message ID | 20210208135609.7685-24-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: stmmac: Fix clocks/reset-related procedures | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Guessing tree name failed - patch did not apply |
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index a8dec219c295..03acf14d76de 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -206,7 +206,12 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) { u32 clk_rate; - clk_rate = clk_get_rate(priv->plat->stmmac_clk); + /* If APB clock has been specified then it is supposed to be used + * to select the CSR mode. Otherwise the application clock is the + * source of the periodic signal for the CSR interface. + */ + clk_rate = clk_get_rate(priv->plat->pclk) ?: + clk_get_rate(priv->plat->stmmac_clk); /* Platform provided default clk_csr would be assumed valid * for all other cases except for the below mentioned ones.
In accordance with [1] the MDC clock frequency is supposed to be selected with respect to the CSR clock frequency. CSR clock can be either tied to the DW MAC system clock (GMAC main clock) or supplied via a dedicated clk_csr_i signal. Current MDC clock selection procedure handles the former case while having no support of the later one. That's wrong for the devices which have separate system and CSR clocks. Let's fix it by first trying to get the synchro-signal rate from the "pclk" clock, if it hasn't been specified then fall-back to the "stmmaceth" clock. [1] DesignWare Cores Ethernet MAC Universal Databook, Revision 3.73a, October 2013, p. 424. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)