@@ -1320,6 +1320,8 @@ const struct stmmac_ops dwmac510_ops = {
.debug = dwmac4_debug,
.set_filter = dwmac4_set_filter,
.safety_feat_config = dwmac5_safety_feat_config,
+ .enable_safety_feat_irq = dwmac5_enable_safety_feat_irq,
+ .disable_safety_feat_irq = dwmac5_disable_safety_feat_irq,
.safety_feat_irq_status = dwmac5_safety_feat_irq_status,
.safety_feat_dump = dwmac5_safety_feat_dump,
.rxp_config = dwmac5_rxp_config,
@@ -190,7 +190,7 @@ int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp)
if (!asp)
return -EINVAL;
- /* 1. Enable Safety Features */
+ /* Enable Safety Features */
value = readl(ioaddr + MTL_ECC_CONTROL);
value |= TSOEE; /* TSO ECC */
value |= MRXPEE; /* MTL RX Parser ECC */
@@ -199,30 +199,17 @@ int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp)
value |= MTXEE; /* MTL TX FIFO ECC */
writel(value, ioaddr + MTL_ECC_CONTROL);
- /* 2. Enable MTL Safety Interrupts */
- value = readl(ioaddr + MTL_ECC_INT_ENABLE);
- value |= RPCEIE; /* RX Parser Memory Correctable Error */
- value |= ECEIE; /* EST Memory Correctable Error */
- value |= RXCEIE; /* RX Memory Correctable Error */
- value |= TXCEIE; /* TX Memory Correctable Error */
- writel(value, ioaddr + MTL_ECC_INT_ENABLE);
-
- /* 3. Enable DMA Safety Interrupts */
- value = readl(ioaddr + DMA_ECC_INT_ENABLE);
- value |= TCEIE; /* TSO Memory Correctable Error */
- writel(value, ioaddr + DMA_ECC_INT_ENABLE);
-
/* Only ECC Protection for External Memory feature is selected */
if (asp <= 0x1)
return 0;
- /* 5. Enable Parity and Timeout for FSM */
+ /* Enable Parity and Timeout for FSM */
value = readl(ioaddr + MAC_FSM_CONTROL);
value |= PRTYEN; /* FSM Parity Feature */
value |= TMOUTEN; /* FSM Timeout Feature */
writel(value, ioaddr + MAC_FSM_CONTROL);
- /* 4. Enable Data Parity Protection */
+ /* Enable Data Parity Protection */
value = readl(ioaddr + MTL_DPP_CONTROL);
value |= EDPP;
writel(value, ioaddr + MTL_DPP_CONTROL);
@@ -239,6 +226,23 @@ int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp)
return 0;
}
+void dwmac5_enable_safety_feat_irq(void __iomem *ioaddr)
+{
+ /* Enable MTL Safety Interrupts: RX Parser Memory, EST, RX and Tx
+ * Memory Correctable Errors.
+ */
+ writel(RPCEIE | ECEIE | RXCEIE | TXCEIE, ioaddr + MTL_ECC_INT_ENABLE);
+
+ /* Enable DMA Safety Interrupts: TSO Memory Correctable Error. */
+ writel(TCEIE, ioaddr + DMA_ECC_INT_ENABLE);
+}
+
+void dwmac5_disable_safety_feat_irq(void __iomem *ioaddr)
+{
+ writel(0, ioaddr + MTL_ECC_INT_ENABLE);
+ writel(0, ioaddr + DMA_ECC_INT_ENABLE);
+}
+
int dwmac5_safety_feat_irq_status(struct net_device *ndev,
void __iomem *ioaddr, unsigned int asp,
struct stmmac_safety_stats *stats)
@@ -99,6 +99,8 @@
#define GMAC_RXQCTRL_VFFQE BIT(16)
int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp);
+void dwmac5_enable_safety_feat_irq(void __iomem *ioaddr);
+void dwmac5_disable_safety_feat_irq(void __iomem *ioaddr);
int dwmac5_safety_feat_irq_status(struct net_device *ndev,
void __iomem *ioaddr, unsigned int asp,
struct stmmac_safety_stats *stats);
@@ -834,28 +834,14 @@ static int dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp)
if (!asp)
return -EINVAL;
- /* 1. Enable Safety Features */
+ /* Enable Safety Features */
writel(0x0, ioaddr + XGMAC_MTL_ECC_CONTROL);
- /* 2. Enable MTL Safety Interrupts */
- value = readl(ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
- value |= XGMAC_RPCEIE; /* RX Parser Memory Correctable Error */
- value |= XGMAC_ECEIE; /* EST Memory Correctable Error */
- value |= XGMAC_RXCEIE; /* RX Memory Correctable Error */
- value |= XGMAC_TXCEIE; /* TX Memory Correctable Error */
- writel(value, ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
-
- /* 3. Enable DMA Safety Interrupts */
- value = readl(ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
- value |= XGMAC_DCEIE; /* Descriptor Cache Memory Correctable Error */
- value |= XGMAC_TCEIE; /* TSO Memory Correctable Error */
- writel(value, ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
-
/* Only ECC Protection for External Memory feature is selected */
if (asp <= 0x1)
return 0;
- /* 4. Enable Parity and Timeout for FSM */
+ /* Enable Parity and Timeout for FSM */
value = readl(ioaddr + XGMAC_MAC_FSM_CONTROL);
value |= XGMAC_PRTYEN; /* FSM Parity Feature */
value |= XGMAC_TMOUTEN; /* FSM Timeout Feature */
@@ -864,6 +850,26 @@ static int dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp)
return 0;
}
+void dwxgmac3_enable_safety_feat_irq(void __iomem *ioaddr)
+{
+ /* Enable MTL Safety Interrupts: RX Parser Memory, EST, RX and Tx
+ * Memory Correctable Errors.
+ */
+ writel(XGMAC_RPCEIE | XGMAC_ECEIE | XGMAC_RXCEIE | XGMAC_TXCEIE,
+ ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
+
+ /* Enable DMA Safety Interrupts: Descriptor Cache, TSO Memory
+ * Correctable Errors.
+ */
+ writel(XGMAC_DCEIE | XGMAC_TCEIE, ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
+}
+
+void dwxgmac3_disable_safety_feat_irq(void __iomem *ioaddr)
+{
+ writel(0, ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
+ writel(0, ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
+}
+
static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev,
void __iomem *ioaddr,
unsigned int asp,
@@ -1510,6 +1516,8 @@ const struct stmmac_ops dwxgmac210_ops = {
.debug = NULL,
.set_filter = dwxgmac2_set_filter,
.safety_feat_config = dwxgmac3_safety_feat_config,
+ .enable_safety_feat_irq = dwxgmac3_enable_safety_feat_irq,
+ .disable_safety_feat_irq = dwxgmac3_disable_safety_feat_irq,
.safety_feat_irq_status = dwxgmac3_safety_feat_irq_status,
.safety_feat_dump = dwxgmac3_safety_feat_dump,
.set_mac_loopback = dwxgmac2_set_mac_loopback,
@@ -365,6 +365,8 @@ struct stmmac_ops {
void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
/* Safety Features */
int (*safety_feat_config)(void __iomem *ioaddr, unsigned int asp);
+ void (*enable_safety_feat_irq)(void __iomem *ioaddr);
+ void (*disable_safety_feat_irq)(void __iomem *ioaddr);
int (*safety_feat_irq_status)(struct net_device *ndev,
void __iomem *ioaddr, unsigned int asp,
struct stmmac_safety_stats *stats);
@@ -482,6 +484,10 @@ struct stmmac_ops {
stmmac_do_void_callback(__priv, mac, pcs_get_adv_lp, __args)
#define stmmac_safety_feat_config(__priv, __args...) \
stmmac_do_callback(__priv, mac, safety_feat_config, __args)
+#define stmmac_enable_safety_feat_irq(__priv, __args...) \
+ stmmac_do_void_callback(__priv, mac, enable_safety_feat_irq, __args)
+#define stmmac_disable_safety_feat_irq(__priv, __args...) \
+ stmmac_do_void_callback(__priv, mac, disable_safety_feat_irq, __args)
#define stmmac_safety_feat_irq_status(__priv, __args...) \
stmmac_do_callback(__priv, mac, safety_feat_irq_status, __args)
#define stmmac_safety_feat_dump(__priv, __args...) \
@@ -4139,6 +4139,9 @@ static void stmmac_enable_irq(struct stmmac_priv *priv)
maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
+ if (priv->dma_cap.asp)
+ stmmac_enable_safety_feat_irq(priv, priv->ioaddr);
+
for (chan = 0; chan < maxq; ++chan) {
stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
@@ -4176,6 +4179,9 @@ static void stmmac_disable_irq(struct stmmac_priv *priv)
stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
}
+ if (priv->dma_cap.asp)
+ stmmac_disable_safety_feat_irq(priv, priv->ioaddr);
+
enable_irq(priv->dev->irq);
}
Safety feature IRQs is another set of IRQs, which aside with the DMA, MAC, MTL, GPIOs, etc interrupts can be generated by the DW *MAC network devices. They are signalled by means of the shared sbd_intr_o lane too, so we need to be able mask/unmask these interrupts in the framework of the generic IRQs setup procedure. Note there is no need in preserving the Safety interrupts enable register content in the provided callbacks as these registers are changed in these methods only. Moreover by doing so we disable the interrupts, which are unsupported by the Safety IRQ status handler, if any of them have been enabled by default. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- Folks, the zero initialization of the DW xGMAC XGMAC_MTL_ECC_CONTROL register looks suspicious. Are you sure it is supposed to be cleared out in order to enable the safety IRQs? --- .../net/ethernet/stmicro/stmmac/dwmac4_core.c | 2 + drivers/net/ethernet/stmicro/stmmac/dwmac5.c | 36 +++++++++-------- drivers/net/ethernet/stmicro/stmmac/dwmac5.h | 2 + .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 40 +++++++++++-------- drivers/net/ethernet/stmicro/stmmac/hwif.h | 6 +++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++ 6 files changed, 60 insertions(+), 32 deletions(-)