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[84.226.167.205]) by smtp.gmail.com with ESMTPSA id m17sm28675495wrx.92.2021.03.10.00.36.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 00:36:08 -0800 (PST) From: Krzysztof Kozlowski List-Id: To: Catalin Marinas , Will Deacon , Dinh Nguyen , Rob Herring , Michael Turquette , Stephen Boyd , Moritz Fischer , Tom Rix , Lee Jones , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-fpga@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, arm@kernel.org, soc@kernel.org, Arnd Bergmann , Olof Johansson Cc: Krzysztof Kozlowski Subject: [RFC v2 2/5] clk: socfpga: build together Stratix 10, Agilex and N5X clock drivers Date: Wed, 10 Mar 2021 09:33:24 +0100 Message-Id: <20210310083327.480837-3-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> References: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC On a multiplatform kernel there is little benefit in splitting each clock driver per platform because space savings are minimal. Such split also complicates the code, especially after adding compile testing. Build all arm64 Intel SoCFPGA clocks together with one entry in Makefile. This also removed duplicated line in the Makefile (selecting common part of clocks per platform). Signed-off-by: Krzysztof Kozlowski --- drivers/clk/socfpga/Kconfig | 8 ++++---- drivers/clk/socfpga/Makefile | 7 +++---- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index cae6fd9fac64..7d4772faf93d 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -config COMMON_CLK_AGILEX +config COMMON_CLK_SOCFPGA64 bool - # Intel Agilex / N5X clock controller support - default y if ARCH_AGILEX || ARCH_N5X - depends on ARCH_AGILEX || ARCH_N5X + # Intel Stratix / Agilex / N5X clock controller support + default y if ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 + depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index e3614f758184..0446240162cf 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o -obj-$(CONFIG_COMMON_CLK_AGILEX) += clk-agilex.o -obj-$(CONFIG_COMMON_CLK_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_COMMON_CLK_SOCFPGA64) += clk-s10.o \ + clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \ + clk-agilex.o