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[193.12.47.89]) by smtp.gmail.com with ESMTPSA id r71sm193430lff.12.2021.04.21.05.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Apr 2021 05:05:00 -0700 (PDT) From: Tobias Waldekranz To: davem@davemloft.net, kuba@kernel.org Cc: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, olteanv@gmail.com, netdev@vger.kernel.org Subject: [PATCH net-next 1/3] net: dsa: mv88e6xxx: Correct spelling of define "ADRR" -> "ADDR" Date: Wed, 21 Apr 2021 14:04:52 +0200 Message-Id: <20210421120454.1541240-2-tobias@waldekranz.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210421120454.1541240-1-tobias@waldekranz.com> References: <20210421120454.1541240-1-tobias@waldekranz.com> MIME-Version: 1.0 Organization: Westermo Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Because ADRR is not a thing. Signed-off-by: Tobias Waldekranz Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/chip.c | 2 +- drivers/net/dsa/mv88e6xxx/global2.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 9ff1a10993b1..eca285aaf72f 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -1440,7 +1440,7 @@ static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) * the special "LAG device" in the PVT, using * the LAG ID as the port number. */ - dev = MV88E6XXX_G2_PVT_ADRR_DEV_TRUNK; + dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; port = dsa_lag_id(dst, dp->lag_dev); } } diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h index c78769cdbb59..8f85c23ec9c7 100644 --- a/drivers/net/dsa/mv88e6xxx/global2.h +++ b/drivers/net/dsa/mv88e6xxx/global2.h @@ -109,7 +109,7 @@ #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff -#define MV88E6XXX_G2_PVT_ADRR_DEV_TRUNK 0x1f +#define MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK 0x1f /* Offset 0x0C: Cross-chip Port VLAN Data Register */ #define MV88E6XXX_G2_PVT_DATA 0x0c