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([103.51.72.31]) by smtp.gmail.com with ESMTPSA id i25sm4581407pfo.20.2021.07.29.13.11.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jul 2021 13:11:55 -0700 (PDT) From: Anand Moon To: netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, devicetree@vger.kernel.org Cc: Anand Moon , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Rob Herring , Kevin Hilman , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Jakub Kicinski , Maxime Coquelin , Philipp Zabel , Emiliano Ingrassia Subject: [PATCHv1 3/3] net: stmmac: dwmac-meson8b: Add reset controller for ethernet phy Date: Fri, 30 Jul 2021 01:40:52 +0530 Message-Id: <20210729201100.3994-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210729201100.3994-1-linux.amoon@gmail.com> References: <20210729201100.3994-1-linux.amoon@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add reset controller for Ethernet phy reset on every boot for Amlogic SoC. Cc: Jerome Brunet Cc: Neil Armstrong Cc: Martin Blumenstingl Signed-off-by: Anand Moon --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index c7a6588d9398..8b3b5e8c2a8a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "stmmac_platform.h" @@ -95,6 +96,7 @@ struct meson8b_dwmac { u32 tx_delay_ns; u32 rx_delay_ps; struct clk *timing_adj_clk; + struct reset_control *eth_reset; }; struct meson8b_dwmac_clk_configs { @@ -384,6 +386,17 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, PRG_ETH0_TX_AND_PHY_REF_CLK); + /* Make sure the Ethernet PHY is properly reseted, as U-Boot may leave + * it at deasserted state, and thus it may fail to reset EMAC. + * + * This assumes the driver has exclusive access to the EPHY reset. + */ + ret = reset_control_reset(dwmac->eth_reset); + if (ret) { + dev_err(dwmac->dev, "Cannot reset internal PHY\n"); + return ret; + } + return 0; } @@ -465,6 +478,13 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } + dwmac->eth_reset = devm_reset_control_get_exclusive(dwmac->dev, "ethreset"); + if (IS_ERR_OR_NULL(dwmac->eth_reset)) { + dev_err(dwmac->dev, "Failed to get Ethernet reset\n"); + ret = PTR_ERR(dwmac->eth_reset); + goto err_remove_config_dt; + } + ret = meson8b_init_rgmii_delays(dwmac); if (ret) goto err_remove_config_dt;