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Wed, 9 Mar 2022 14:38:25 +0000 From: Ioana Ciornei To: davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org Cc: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, leoyang.li@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Ioana Ciornei Subject: [PATCH net-next 8/8] arch: arm64: dts: lx2160a: describe the SerDes block #1 Date: Wed, 9 Mar 2022 16:37:51 +0200 Message-Id: <20220309143751.3362678-9-ioana.ciornei@nxp.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220309143751.3362678-1-ioana.ciornei@nxp.com> References: <20220309143751.3362678-1-ioana.ciornei@nxp.com> X-ClientProxiedBy: AM0PR02CA0187.eurprd02.prod.outlook.com (2603:10a6:20b:28e::24) To AM9PR04MB8555.eurprd04.prod.outlook.com (2603:10a6:20b:436::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 93f1b9cd-a9bd-449c-d75f-08da01da77a5 X-MS-TrafficTypeDiagnostic: VI1PR04MB6223:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This way, the ethernet nodes can each reference their serdes lanes individually using the 'phys' dts property. Signed-off-by: Ioana Ciornei --- .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 ++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 41 +++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index 17f8e733972a..14a6334adff2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -63,21 +63,25 @@ sfp3: sfp-3 { &dpmac7 { sfp = <&sfp0>; managed = "in-band-status"; + phys = <&serdes1_lane_d>; }; &dpmac8 { sfp = <&sfp1>; managed = "in-band-status"; + phys = <&serdes1_lane_c>; }; &dpmac9 { sfp = <&sfp2>; managed = "in-band-status"; + phys = <&serdes1_lane_b>; }; &dpmac10 { sfp = <&sfp3>; managed = "in-band-status"; + phys = <&serdes1_lane_a>; }; &emdio2 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 7032505f5ef3..04f29c086512 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -612,6 +612,47 @@ soc { ranges; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + serdes_1: serdes_phy@1ea0000 { + compatible = "fsl,lynx-28g"; + reg = <0x00 0x1ea0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + serdes1_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + serdes1_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + serdes1_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + serdes1_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; + }; + crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <10>;