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[82.81.222.124]) by smtp.gmail.com with ESMTPSA id f8-20020a5d64c8000000b0020784359295sm12839196wri.54.2022.04.10.03.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Apr 2022 03:47:22 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Michael Hennerich , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , Paolo Abeni Subject: [PATCH 2/3] net: phy: adin: add support for 125MHz clk-out Date: Sun, 10 Apr 2022 13:46:25 +0300 Message-Id: <20220410104626.11517-3-josua@solid-run.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220410104626.11517-1-josua@solid-run.com> References: <20220410104626.11517-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The ADIN1300 supports generating certain clocks on its GP_CLK pin. Add support for selecting the 125MHz clock via a device-tree property. While other frequencies are technically available, they are omitted for now, due to the complexity of choices. Co-developed-by: Alvaro Karsz Signed-off-by: Alvaro Karsz Signed-off-by: Josua Mayer --- drivers/net/phy/adin.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index 5ce6da62cc8e..dbe2bb7f30d9 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -99,6 +99,10 @@ #define ADIN1300_GE_SOFT_RESET_REG 0xff0c #define ADIN1300_GE_SOFT_RESET BIT(0) +#define ADIN1300_GE_CLK_CFG_REG 0xff1f +#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0) +#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4) + #define ADIN1300_GE_RGMII_CFG_REG 0xff23 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) #define ADIN1300_GE_RGMII_RX_SEL(x) \ @@ -433,6 +437,28 @@ static int adin_set_tunable(struct phy_device *phydev, } } +static int adin_config_clk_out(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + u32 val; + u8 sel; + + if (device_property_read_u32(dev, "adi,clk-out-frequency", &val)) + return 0; + + switch (val) { + case 125000000: + sel = ADIN1300_GE_CLK_CFG_FREE_125; + break; + default: + phydev_err(phydev, "invalid adi,clk-out-frequency\n"); + return -EINVAL; + } + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG, + ADIN1300_GE_CLK_CFG_MASK, sel); +} + static int adin_config_init(struct phy_device *phydev) { int rc; @@ -455,6 +481,10 @@ static int adin_config_init(struct phy_device *phydev) if (rc < 0) return rc; + rc = adin_config_clk_out(phydev); + if (rc < 0) + return rc; + phydev_dbg(phydev, "PHY is using mode '%s'\n", phy_modes(phydev->interface));