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Miller" , Jakub Kicinski , Madalin Bucur , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Paolo Abeni , Russell King , Eric Dumazet , Sean Anderson , Krzysztof Kozlowski , Li Yang , Rob Herring , Shawn Guo , devicetree@vger.kernel.org Subject: [PATCH net-next 26/28] arm64: dts: ls1046ardb: Add serdes bindings Date: Fri, 17 Jun 2022 16:33:10 -0400 Message-Id: <20220617203312.3799646-27-sean.anderson@seco.com> X-Mailer: git-send-email 2.35.1.1320.gc452695387.dirty In-Reply-To: <20220617203312.3799646-1-sean.anderson@seco.com> References: <20220617203312.3799646-1-sean.anderson@seco.com> X-ClientProxiedBy: BL1PR13CA0384.namprd13.prod.outlook.com (2603:10b6:208:2c0::29) To VI1PR03MB4973.eurprd03.prod.outlook.com (2603:10a6:803:c5::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7d4e5ddf-79f5-461a-2581-08da50a0c525 X-MS-TrafficTypeDiagnostic: AS8PR03MB6838:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is no driver for this device (and as far as I know all you can do with the 100MHz clocks is gate them), so I have chosen to model it as a single fixed clock. Note: the SerDes1 lane numbering for the LS1046A is *reversed*. This means that Lane A (what the driver thinks is lane 0) uses pins SD1_TX3_P/N. Signed-off-by: Sean Anderson --- .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 7025aad8ae89..21a153349359 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -26,6 +26,30 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + clocks { + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + }; +}; + +&serdes1 { + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; +}; + +&serdes2 { + clocks = <&clk_100mhz>, <&clk_100mhz>; + clock-names = "ref0", "ref1"; }; &duart0 { @@ -140,21 +164,29 @@ ethernet@e6000 { ethernet@e8000 { phy-handle = <&sgmii_phy1>; phy-connection-type = "sgmii"; + phys = <&serdes1 1 1>; + phy-names = "serdes"; }; ethernet@ea000 { phy-handle = <&sgmii_phy2>; phy-connection-type = "sgmii"; + phys = <&serdes1 0 0>; + phy-names = "serdes"; }; ethernet@f0000 { /* 10GEC1 */ phy-handle = <&aqr106_phy>; phy-connection-type = "xgmii"; + phys = <&serdes1 3 3>; + phy-names = "serdes"; }; ethernet@f2000 { /* 10GEC2 */ fixed-link = <0 1 1000 0 0>; phy-connection-type = "xgmii"; + phys = <&serdes1 2 2>; + phy-names = "serdes"; }; mdio@fc000 {