| Message ID | 20220624144001.95518-7-clement.leger@bootlin.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 8956e96c1d4d46c58dd10f7da1a20da66f96ef48 |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | add support for Renesas RZ/N1 ethernet subsystem devices | expand |
Hi Clément, On Fri, Jun 24, 2022 at 4:41 PM Clément Léger <clement.leger@bootlin.com> wrote: > Add bindings for Renesas RZ/N1 Advanced 5 port switch. This switch is > present on Renesas RZ/N1 SoC and was probably provided by MoreThanIP. > This company does not exists anymore and has been bought by Synopsys. > Since this IP can't be find anymore in the Synospsy portfolio, lets use > Renesas as the vendor compatible for this IP. > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml > @@ -0,0 +1,134 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/N1 Advanced 5 ports ethernet switch > + > +maintainers: > + - Clément Léger <clement.leger@bootlin.com> > + > +description: | > + The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and > + handles 4 ports + 1 CPU management port. While diving deeper into the RZ/N1 documentation, I noticed the switch has 4 interrupts, which are currently not described in the bindings. Presumably the driver has no need to use them, but as DT describes hardware, I think it would be good to submit follow-up patches for bindings and DTS to add the interrupts. Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Le Tue, 28 Jun 2022 17:37:57 +0200, Geert Uytterhoeven <geert@linux-m68k.org> a écrit : > > +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml > > @@ -0,0 +1,134 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/N1 Advanced 5 ports ethernet switch > > + > > +maintainers: > > + - Clément Léger <clement.leger@bootlin.com> > > + > > +description: | > > + The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and > > + handles 4 ports + 1 CPU management port. > > While diving deeper into the RZ/N1 documentation, I noticed the switch > has 4 interrupts, which are currently not described in the bindings. > Presumably the driver has no need to use them, but as DT describes > hardware, I think it would be good to submit follow-up patches for > bindings and DTS to add the interrupts. Noted ;) Clément > > Thanks! > > Gr{oetje,eeting}s,
diff --git a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml new file mode 100644 index 000000000000..103b1ef5af1b --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Advanced 5 ports ethernet switch + +maintainers: + - Clément Léger <clement.leger@bootlin.com> + +description: | + The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and + handles 4 ports + 1 CPU management port. + +allOf: + - $ref: dsa.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-a5psw + - const: renesas,rzn1-a5psw + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + + clocks: + items: + - description: AHB clock used for the switch register interface + - description: Switch system clock + + clock-names: + items: + - const: hclk + - const: clk + + ethernet-ports: + type: object + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^(ethernet-)?port@[0-4]$": + type: object + description: Ethernet switch ports + + properties: + pcs-handle: + description: + phandle pointing to a PCS sub-node compatible with + renesas,rzn1-miic.yaml# + $ref: /schemas/types.yaml#/definitions/phandle + +unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + + switch@44050000 { + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; + reg = <0x44050000 0x10000>; + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>; + clock-names = "hclk", "clk"; + power-domains = <&sysctrl>; + + dsa,member = <0 0>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&switch0phy3>; + pcs-handle = <&mii_conv4>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&switch0phy1>; + pcs-handle = <&mii_conv3>; + }; + + port@4 { + reg = <4>; + ethernet = <&gmac2>; + label = "cpu"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>; + reset-delay-us = <15>; + clock-frequency = <2500000>; + + switch0phy1: ethernet-phy@1{ + reg = <1>; + }; + + switch0phy3: ethernet-phy@3{ + reg = <3>; + }; + }; + };