| Message ID | 20220704101056.24821-3-wei.fang@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Add the fec node on i.MX8ULP platform | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
Hello Wei, On 04.07.22 12:10, Wei Fang wrote: > + clock_ext_rmii: clock-ext-rmii { > + compatible = "fixed-clock"; > + clock-frequency = <50000000>; > + #clock-cells = <0>; > + clock-output-names = "ext_rmii_clk"; > + }; > + > + clock_ext_ts: clock-ext-ts { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "ext_ts_clk"; > + }; How are these SoC-specific? They sound like they belong into board DT. > + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, > + <&pcc4 IMX8ULP_CLK_ENET>, > + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, > + <&clock_ext_rmii>; > + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; I think the default should be the other way round, assume MAC to provide reference clock and allow override on board-level if PHY does it instead. Cheers, Ahmad
> > + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, > > + <&pcc4 IMX8ULP_CLK_ENET>, > > + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, > > + <&clock_ext_rmii>; > > + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; > > I think the default should be the other way round, assume MAC to provide reference > clock and allow override on board-level if PHY does it instead. I would make it the same as all the other instances of FEC in the IMX7, IMX6, IMX5, IMX4, Vybrid etc Andrew
Hi Ahmad: Thanks for your reply. clock_ext_rmii and clock_ext_ts indeed belong into board DT, I will move them to imx.8ulp-evk.dts and resubmit the patch. And refer to imx8ulp reference manual, the enet_clk_ref only has external clock source, so it is related to specifical board. Therefore, can I delete the enet_clk_ref clock in imx8ulp.dtsi (as shown below) and override the clock and clock-names properties in imx8ulp-evk.dts ? > + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, > + <&pcc4 IMX8ULP_CLK_ENET>, > + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; > + clock-names = "ipg", "ahb", "ptp"; -----Original Message----- From: Ahmad Fatoum <a.fatoum@pengutronix.de> Sent: 2022年7月4日 15:07 To: Wei Fang <wei.fang@nxp.com>; davem@davemloft.net; edumazet@google.com; kuba@kernel.org; pabeni@redhat.com; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; shawnguo@kernel.org; s.hauer@pengutronix.de Cc: Aisheng Dong <aisheng.dong@nxp.com>; devicetree@vger.kernel.org; Peng Fan <peng.fan@nxp.com>; Jacky Bai <ping.bai@nxp.com>; netdev@vger.kernel.org; linux-kernel@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; kernel@pengutronix.de; sudeep.holla@arm.com; festevam@gmail.com; linux-arm-kernel@lists.infradead.org Subject: [EXT] Re: [PATCH 2/3] arm64: dts: imx8ulp: Add the fec support Caution: EXT Email Hello Wei, On 04.07.22 12:10, Wei Fang wrote: > + clock_ext_rmii: clock-ext-rmii { > + compatible = "fixed-clock"; > + clock-frequency = <50000000>; > + #clock-cells = <0>; > + clock-output-names = "ext_rmii_clk"; > + }; > + > + clock_ext_ts: clock-ext-ts { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "ext_ts_clk"; > + }; How are these SoC-specific? They sound like they belong into board DT. > + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, > + <&pcc4 IMX8ULP_CLK_ENET>, > + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, > + <&clock_ext_rmii>; > + clock-names = "ipg", "ahb", "ptp", > + "enet_clk_ref"; I think the default should be the other way round, assume MAC to provide reference clock and allow override on board-level if PHY does it instead. Cheers, Ahmad -- Pengutronix e.K. | | Steuerwalder Str. 21 | https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&data=05%7C01%7Cwei.fang%40nxp.com%7C9dad0367d54b427c5e8008da5d8bd912%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637925152473535653%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=3tkqsToqq7%2BvNDkC7ZaMm0DsisugDpkVQXCr2zqPbF8%3D&reserved=0 | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 60c1b018bf03..822f3aea46e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -16,6 +16,7 @@ / { #size-cells = <2>; aliases { + ethernet0 = &fec; gpio0 = &gpiod; gpio1 = &gpioe; gpio2 = &gpiof; @@ -137,6 +138,19 @@ scmi_sensor: protocol@15 { }; }; + clock_ext_rmii: clock-ext-rmii { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + clock-output-names = "ext_rmii_clk"; + }; + + clock_ext_ts: clock-ext-ts { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "ext_ts_clk"; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -365,6 +379,21 @@ usdhc2: mmc@298f0000 { bus-width = <4>; status = "disabled"; }; + + fec: ethernet@29950000 { + compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec"; + reg = <0x29950000 0x10000>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0"; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&pcc4 IMX8ULP_CLK_ENET>, + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, + <&clock_ext_rmii>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + fsl,num-tx-queues = <1>; + fsl,num-rx-queues = <1>; + status = "disabled"; + }; }; gpioe: gpio@2d000080 {
Add the fec support on i.MX8ULP platforms. Signed-off-by: Wei Fang <wei.fang@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+)