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Miller" , Eric Dumazet , Paolo Abeni , , Saeed Mahameed , Gal Pressman , Tariq Toukan , Gal Pressman Subject: [PATCH net-next V2 3/6] net/mlx5e: kTLS, Introduce TLS-specific create TIS Date: Wed, 13 Jul 2022 08:16:00 +0300 Message-ID: <20220713051603.14014-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220713051603.14014-1-tariqt@nvidia.com> References: <20220713051603.14014-1-tariqt@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e93d591d-1faf-43de-6a47-08da648ee440 X-MS-TrafficTypeDiagnostic: DM5PR12MB1915:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: R7D8cPiXOExhgj38QKHnXlJOcMzFtc0pzXtA2zcq8IOLB5Z0dOPEN6+T0ySoFZi9Ty4pU1nWJU5MHD0FQru2DbDrbjJ0FY+a2VZXlT6Q7IgpN59UQeW0pT/br0HFaMiKJNXrazg1qLZINrbFUj6SD7Ec11XG/zj++nDw+gkhd9/qe6vd+FRJTLmEspZJnhxX6D1gG5wk2bBKoZ90g/INZ81shKgjSkj3D3G/+q1EusLscTqdu6BGDSR7Wveg9KrU7+FHcHUew0cevQh1KLv+hh/sLtQSzpb4IvYGrCPJQHy96jb4P/6eIEqoNbG1BD2El3GyS3AsvWCb7dRiIn9IU8kkNRgcB21DofFr2WUt16S1WSwLy16Igh9wBk6KiQgiA8i19Vj3fxU7sqDMvrxU8VqL0L+gGt8r4ILwdTpozU0Yg7dvRVUM2uUyiuASTTMGwcn4y3nCu8yFQSpTfsjQ2mE39kom47m4UvDVS1Fjv47aJtjJwup1uH/MyMKYwQPG/qeiKzj5qrTB0bltQcRd8qfhF7gfBDMP6vpkztDy696UJeXNtSG/sl1I+U7nP0yX0QKWAq8mRFN+2fjHAAr76AQFJT6MTh/XJVHU/UG45IYDqPeeuV0XiYl1eXSXsqXp+GaEk+H69nIMbdxZ/strZkI+HHnsmvDsTEO1JrwG95HxTJrjoIVJ67ifWQfYoQVzO8Cba5ygrKx5nlPMD2fWScN0H3np9q7UxitWP0ncPt9auH7dx6KTX6/Brhw9DrUNvM3jCxu6rdmXn5IEXzh9rgfQVZTQmBfG7aFxhgOdJCkBFhSshKna4nO4JF6Nw3q6e2rpg05BjHJA2zy28TFaNpbToDeszajH00LQp3UMysI= X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(396003)(376002)(346002)(136003)(39860400002)(36840700001)(40470700004)(46966006)(82740400003)(356005)(478600001)(107886003)(2616005)(5660300002)(36756003)(26005)(8936002)(86362001)(6666004)(41300700001)(2906002)(82310400005)(7696005)(186003)(40460700003)(4326008)(36860700001)(426003)(83380400001)(1076003)(47076005)(54906003)(70586007)(110136005)(70206006)(316002)(40480700001)(8676002)(81166007)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jul 2022 05:16:50.2032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e93d591d-1faf-43de-6a47-08da648ee440 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1915 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org TLS TIS objects have a defined role in mapping and reaching the HW TLS contexts. Some standard TIS attributes (like LAG port affinity) are not relevant for them. Use a dedicated TLS TIS create function instead of the generic mlx5e_create_tis. Signed-off-by: Tariq Toukan Reviewed-by: Gal Pressman Signed-off-by: Saeed Mahameed --- .../ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c index cc5cb3010e64..2cd0437666d2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c @@ -39,16 +39,20 @@ u16 mlx5e_ktls_get_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_params *pa return stop_room; } +static void mlx5e_ktls_set_tisc(struct mlx5_core_dev *mdev, void *tisc) +{ + MLX5_SET(tisc, tisc, tls_en, 1); + MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn); + MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn); +} + static int mlx5e_ktls_create_tis(struct mlx5_core_dev *mdev, u32 *tisn) { u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; - void *tisc; - - tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); - MLX5_SET(tisc, tisc, tls_en, 1); + mlx5e_ktls_set_tisc(mdev, MLX5_ADDR_OF(create_tis_in, in, ctx)); - return mlx5e_create_tis(mdev, in, tisn); + return mlx5_core_create_tis(mdev, in, tisn); } struct mlx5e_ktls_offload_context_tx {