Message ID | 20220818222742.1070935-8-jacob.e.keller@intel.com (mailing list archive) |
---|---|
State | Changes Requested |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | ptp: convert drivers to .adjfine | expand |
Context | Check | Description |
---|---|---|
netdev/tree_selection | success | Clearly marked for net-next |
netdev/fixes_present | success | Fixes tag not required for -next series |
netdev/subject_prefix | success | Link |
netdev/cover_letter | success | Series has a cover letter |
netdev/patch_count | success | Link |
netdev/header_inline | success | No static functions without inline keyword in header files |
netdev/build_32bit | success | Errors and warnings before: 85 this patch: 85 |
netdev/cc_maintainers | success | CCed 10 of 10 maintainers |
netdev/build_clang | success | Errors and warnings before: 0 this patch: 0 |
netdev/module_param | success | Was 0 now: 0 |
netdev/verify_signedoff | success | Signed-off-by tag matches author and committer |
netdev/check_selftest | success | No net selftest shell script |
netdev/verify_fixes | success | No Fixes tag |
netdev/build_allmodconfig_warn | success | Errors and warnings before: 85 this patch: 85 |
netdev/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 47 lines checked |
netdev/kdoc | success | Errors and warnings before: 0 this patch: 0 |
netdev/source_inline | success | Was 0 now: 0 |
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c index a40b1583f114..80a2a0073d97 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c @@ -22,28 +22,16 @@ static int hclge_ptp_get_cycle(struct hclge_dev *hdev) return 0; } -static int hclge_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) +static int hclge_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) { struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp); struct hclge_ptp_cycle *cycle = &hdev->ptp->cycle; - u64 adj_val, adj_base, diff; + u64 adj_val, adj_base; unsigned long flags; - bool is_neg = false; u32 quo, numerator; - if (ppb < 0) { - ppb = -ppb; - is_neg = true; - } - adj_base = (u64)cycle->quo * (u64)cycle->den + (u64)cycle->numer; - adj_val = adj_base * ppb; - diff = div_u64(adj_val, 1000000000ULL); - - if (is_neg) - adj_val = adj_base - diff; - else - adj_val = adj_base + diff; + adj_val = adjust_by_scaled_ppm(adj_base, scaled_ppm); /* This clock cycle is defined by three part: quotient, numerator * and denominator. For example, 2.5ns, the quotient is 2, @@ -446,7 +434,7 @@ static int hclge_ptp_create_clock(struct hclge_dev *hdev) ptp->info.max_adj = HCLGE_PTP_CYCLE_ADJ_MAX; ptp->info.n_ext_ts = 0; ptp->info.pps = 0; - ptp->info.adjfreq = hclge_ptp_adjfreq; + ptp->info.adjfine = hclge_ptp_adjfine; ptp->info.adjtime = hclge_ptp_adjtime; ptp->info.gettimex64 = hclge_ptp_gettimex; ptp->info.settime64 = hclge_ptp_settime; @@ -504,7 +492,7 @@ int hclge_ptp_init(struct hclge_dev *hdev) goto out; set_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags); - ret = hclge_ptp_adjfreq(&hdev->ptp->info, 0); + ret = hclge_ptp_adjfine(&hdev->ptp->info, 0); if (ret) { dev_err(&hdev->pdev->dev, "failed to init freq, ret = %d\n", ret);
The hclge implementation of .adjfreq is implemented in terms of a straight forward "base * ppb / 1 billion" calculation. Convert this driver to the .adjfine implementation and use adjust_by_scaled_ppm to calculate the new adjustment value. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Cc: Yisen Zhuang <yisen.zhuang@huawei.com> Cc: Salil Mehta <salil.mehta@huawei.com> Cc: Jie Wang <wangjie125@huawei.com> --- I do not have this hardware, and have only compile tested the change. .../hisilicon/hns3/hns3pf/hclge_ptp.c | 22 +++++-------------- 1 file changed, 5 insertions(+), 17 deletions(-)