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Fri, 19 Aug 2022 07:47:43 +0000 From: wei.fang@nxp.com To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/2] dt-bindings: net: tja11xx: add nxp,refclk_in property Date: Fri, 19 Aug 2022 15:47:27 +0800 Message-Id: <20220819074729.1496088-2-wei.fang@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819074729.1496088-1-wei.fang@nxp.com> References: <20220819074729.1496088-1-wei.fang@nxp.com> X-ClientProxiedBy: SG2PR03CA0122.apcprd03.prod.outlook.com (2603:1096:4:91::26) To DB9PR04MB8106.eurprd04.prod.outlook.com (2603:10a6:10:24b::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ec6961f1-3478-477b-ac13-08da81b71972 X-MS-TrafficTypeDiagnostic: VI1PR04MB7199:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This patch add the property to make the REF_CLK can be configurable. Signed-off-by: Wei Fang --- .../devicetree/bindings/net/nxp,tja11xx.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml index d51da24f3505..c51ee52033e8 100644 --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml @@ -31,6 +31,22 @@ patternProperties: description: The ID number for the child PHY. Should be +1 of parent PHY. + nxp,rmii_refclk_in: + type: boolean + description: | + The REF_CLK is provided for both transmitted and receivced data + in RMII mode. This clock signal is provided by the PHY and is + typically derived from an external 25MHz crystal. Alternatively, + a 50MHz clock signal generated by an external oscillator can be + connected to pin REF_CLK. A third option is to connect a 25MHz + clock to pin CLK_IN_OUT. So, the REF_CLK should be configured + as input or output according to the actual circuit connection. + If present, indicates that the REF_CLK will be configured as + interface reference clock input when RMII mode enabled. + If not present, the REF_CLK will be configured as interface + reference clock output when RMII mode enabled. + Only supported on TJA1100 and TJA1101. + required: - reg @@ -44,6 +60,7 @@ examples: tja1101_phy0: ethernet-phy@4 { reg = <0x4>; + nxp,rmii_refclk_in; }; }; - |