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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 7/8] mfd: ocelot: add regmaps for ocelot_ext Date: Sun, 11 Sep 2022 13:02:43 -0700 Message-Id: <20220911200244.549029-8-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220911200244.549029-1-colin.foster@in-advantage.com> References: <20220911200244.549029-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR03CA0318.namprd03.prod.outlook.com (2603:10b6:303:dd::23) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 411269ed-8e74-4608-ae74-08da94309f5c X-MS-TrafficTypeDiagnostic: BN0PR10MB5335:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oZuCdRCmVBBXTgR0uWD7xyRAO40MryP/7D7XQsKb7gLKyghDXnvLo2jDtqS7sYgphJwf82Sj59I5B+6jy7PGiB7GN6wRf5nQ74E/EUCbXkrMfs+cHiPPyA51QvapR6+ShCEZRWm3qaEJVgPsPjIBgy4d3rMD4m+HfGTuPBuOLUv8RoUn9EG0uvQM1cnoNpf4U9rdJ1IxRWtndh+w7u7hFpyOJvEpeEg9Obml2JQoepmIAV4SWkebptod1Jw+IlxypjeQns1aFm3Hb1ZDKRMxpdosjy5uyfM9+QLXgsvprZMYj4hQ7xWLbaBxtJ8gQJRnL9/01Z+ooBHeUG73HqiBvsczRpXX2zbdKTwIXeUmUVnwXQntw5hpk0kagvUfAU0Q/ugbH9R87JxC8z2ZnVWHW2NE7lgQ5BvHOnoIiORKT5azZD/GHQ8ouRnTY4i+Xl3Mi9P7kheVMLa4+RG7mdG5pviONQPSR4Bwg7XinNzv0CkMaYA4/RkP7GhEB8bJfJ7FpPf97ja4illAHUDcKAa3ujlpiZueoivjts7jstUgEA3OamohaWgPHr/DhZLyQQAcxXpO52YhYgjG16Hu1tIi0rav/fVekDjyYWTfrIpJxNm+ZZvlSTSe+fbzND/szDW0XLFZ70hjcLF4cgRZ4yPJVNPGsjAKgrJuHZVIymUHY4iKatZ54bm1iQX/k8IUGeFy9n6+k82e5ABChhSlvWEr5MW0L7KRCUY7v59lgmTiXul5gWDXyB04jic1sa5v+YdHMtdlJKTL8cZytj0HTI5XOQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(396003)(136003)(366004)(39830400003)(376002)(346002)(38350700002)(38100700002)(8676002)(4326008)(66946007)(36756003)(86362001)(66556008)(66476007)(2906002)(83380400001)(186003)(2616005)(6512007)(6506007)(1076003)(52116002)(478600001)(6486002)(6666004)(26005)(316002)(54906003)(44832011)(41300700001)(8936002)(5660300002)(7416002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nZA4ZNXE/GHMPNx1Ms7D/onahZAodHQzvE+hcEzybbuUL9QdbPbLoVJAuKCc+SFOl6kQczvNKljlMz+JX+cXK1yT1OsXoEJ82LhAc11bKs/NMKkQzLcX7Q1VSTYhkX4jP82rlzGVUKcytZ22geARyikAdk/7+TO1GmnJ9xMIL0G3cV83IEXSirJNIaifosvpYfnJed42PUmInRz1mqcNF7175wVRBxMP3VbfjlKSNoAFL5kpRK1Iv+/rnJdypo+PtwLpF1OyVkw24JEfEpaBxKzfl+BKPS7M9ME78Phjojrw0shO1ShZGysX5Ji6Iq7OW+VIWFamMWYjXVZvZXFDddpf4XkqhR1VjYAmWBo72a4N9x+/TR0d6eKon31ricDZueAI7SoJJtK34wohraYueBWx/iD2FvEIg9R7fukgcpsFuexe7hYADCCu27FIkE1+IhUfexncpvE7No0/1LvRxFUD8SJNuuBaFk/WwWqb4kU6mv8AkWSWD4TY0F5kmroklQ0pPvg+v6z4sDKl/6gFZOaEqQkCjSdVJN/yeJKEwn6ZQBy/AxqxBU6nwxV0vnh/YeHhpKj9jbtFltLQeNlhbCWgG3CoqshVuR1h80n9rjHSZ+kxG+dZltq9vuoC0JO5w7dOHlVvB3xevE9/m+Vq9T3NUQmDYq7M93nvm0ZJg+JbB4Ig20SeEua1LhhUM5iX4aTZIbanguPdO0A0XFVt/ksAArxlyBnwYOrLG3SpwF8kFYodYo6b4mB3SE8WFAy3TQuGq64PRQQ2B/yIzMV6CQFXwD2kGR3pK0myazZlPyn+9KyKxBcssewDYEqFBSsnRbI1SiOrJYUEYCMqZ50uMUWuKojunDvXxaAHW1e3GSYT1cgXizrsz5QYzZcOOPtq5CAKyvwiBINlAfJOZf+Ke7J0CBuMEj7kMed+Safnm4rJ5Zrbu1qgQGGPWeMmOdo/L5cwPZMo1S3HojAMws2B17eZ1p/paM8dzePRZMXfxHsuckYviGtJbZiz5E0dLnJ/e3XpXu7jbZxrDZYnKkVlLfgtPRE/DRlP2SrkcxzoC8h+WfVTFsWbfi/wsW9LZSNs25PIsJcJ23idnwyzcytCnSpI8xtUEk1yT9JqSwl6Vfghn546K3ZBYWiKMDTiRNHuP0Z8NKmFGZUB9B30bYyzpRi8+Dwf+BdvinBOFY4e3ZHiArHqk+Wc90xoi+Wv/4O6m+h/HG7dWGzOGtdmtJRbR9aBsyhIMTg9v3Q0qsjqRXzeA3A9uOzYzmwv0kQ8v71QK7iUQyXRHYLd4XClVjoO/gSJGqF5W5eqw6PBIEsG6Cq9Jg2OiRK4bf9C409XUMKD8E1YV5XSrypYJwNQt6kpkVvRYzY1H4OL9b3hlaEP8hQWiVfkNpz+iSqsldg8YBoc391+NcUOGUQwKPk4do2M273PkYYukoj3jkoDTyDwQGmFJBi60M2toJchWxv4DR0Q2OY22lL2ll4P3ILDQ2cp3z8OHvTL9SaLNd3UBK5GWf4LmrvSpzW3KMBTyxHdJS9stBycwNYOR+c/ET8CONKAz8YwybN2kWeRzwc33SE3xN2vKE5i1YNz1n3TzlWdNaOSBAxkuk53XenhUWFx5IwmxQ== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 411269ed-8e74-4608-ae74-08da94309f5c X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2022 20:02:58.0901 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2mZWWhUm8uZbRC6cESMlZK0/660TCP5rdXT6Ykc+PI67i82EOwjVyNJQK+qGDgzdQSqrzdPGlBoIq+4ncyZaUa0HqsLKVVLqXjRujSTbpOk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5335 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The Ocelot switch core driver relies heavily on a fixed array of resources for both ports and peripherals. This is in contrast to existing peripherals - pinctrl for example - which have a one-to-one mapping of driver <> resource. As such, these regmaps must be created differently so that enumeration-based offsets are preserved. Register the regmaps to the core MFD device unconditionally so they can be referenced by the Ocelot switch / Felix DSA systems. Signed-off-by: Colin Foster --- v1 from previous RFC: * New patch --- drivers/mfd/ocelot-core.c | 88 +++++++++++++++++++++++++++++++++++--- include/linux/mfd/ocelot.h | 5 +++ 2 files changed, 88 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index 1816d52c65c5..aa7fa21b354c 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -34,16 +34,55 @@ #define VSC7512_MIIM0_RES_START 0x7107009c #define VSC7512_MIIM1_RES_START 0x710700c0 -#define VSC7512_MIIM_RES_SIZE 0x024 +#define VSC7512_MIIM_RES_SIZE 0x00000024 #define VSC7512_PHY_RES_START 0x710700f0 -#define VSC7512_PHY_RES_SIZE 0x004 +#define VSC7512_PHY_RES_SIZE 0x00000004 #define VSC7512_GPIO_RES_START 0x71070034 -#define VSC7512_GPIO_RES_SIZE 0x06c +#define VSC7512_GPIO_RES_SIZE 0x0000006c #define VSC7512_SIO_CTRL_RES_START 0x710700f8 -#define VSC7512_SIO_CTRL_RES_SIZE 0x100 +#define VSC7512_SIO_CTRL_RES_SIZE 0x00000100 + +#define VSC7512_HSIO_RES_START 0x710d0000 +#define VSC7512_HSIO_RES_SIZE 0x00000128 + +#define VSC7512_ANA_RES_START 0x71880000 +#define VSC7512_ANA_RES_SIZE 0x00010000 + +#define VSC7512_QS_RES_START 0x71080000 +#define VSC7512_QS_RES_SIZE 0x00000100 + +#define VSC7512_QSYS_RES_START 0x71800000 +#define VSC7512_QSYS_RES_SIZE 0x00200000 + +#define VSC7512_REW_RES_START 0x71030000 +#define VSC7512_REW_RES_SIZE 0x00010000 + +#define VSC7512_SYS_RES_START 0x71010000 +#define VSC7512_SYS_RES_SIZE 0x00010000 + +#define VSC7512_S0_RES_START 0x71040000 +#define VSC7512_S1_RES_START 0x71050000 +#define VSC7512_S2_RES_START 0x71060000 +#define VSC7512_S_RES_SIZE 0x00000400 + +#define VSC7512_GCB_RES_START 0x71070000 +#define VSC7512_GCB_RES_SIZE 0x0000022c + +#define VSC7512_PORT_0_RES_START 0x711e0000 +#define VSC7512_PORT_1_RES_START 0x711f0000 +#define VSC7512_PORT_2_RES_START 0x71200000 +#define VSC7512_PORT_3_RES_START 0x71210000 +#define VSC7512_PORT_4_RES_START 0x71220000 +#define VSC7512_PORT_5_RES_START 0x71230000 +#define VSC7512_PORT_6_RES_START 0x71240000 +#define VSC7512_PORT_7_RES_START 0x71250000 +#define VSC7512_PORT_8_RES_START 0x71260000 +#define VSC7512_PORT_9_RES_START 0x71270000 +#define VSC7512_PORT_10_RES_START 0x71280000 +#define VSC7512_PORT_RES_SIZE 0x00010000 #define VSC7512_GCB_RST_SLEEP_US 100 #define VSC7512_GCB_RST_TIMEOUT_US 100000 @@ -96,6 +135,34 @@ static const struct resource vsc7512_sgpio_resources[] = { DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"), }; +const struct resource vsc7512_target_io_res[TARGET_MAX] = { + [ANA] = DEFINE_RES_REG_NAMED(VSC7512_ANA_RES_START, VSC7512_ANA_RES_SIZE, "ana"), + [QS] = DEFINE_RES_REG_NAMED(VSC7512_QS_RES_START, VSC7512_QS_RES_SIZE, "qs"), + [QSYS] = DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, "qsys"), + [REW] = DEFINE_RES_REG_NAMED(VSC7512_REW_RES_START, VSC7512_REW_RES_SIZE, "rew"), + [SYS] = DEFINE_RES_REG_NAMED(VSC7512_SYS_RES_START, VSC7512_SYS_RES_SIZE, "sys"), + [S0] = DEFINE_RES_REG_NAMED(VSC7512_S0_RES_START, VSC7512_S_RES_SIZE, "s0"), + [S1] = DEFINE_RES_REG_NAMED(VSC7512_S1_RES_START, VSC7512_S_RES_SIZE, "s1"), + [S2] = DEFINE_RES_REG_NAMED(VSC7512_S2_RES_START, VSC7512_S_RES_SIZE, "s2"), + [GCB] = DEFINE_RES_REG_NAMED(VSC7512_GCB_RES_START, VSC7512_GCB_RES_SIZE, "devcpu_gcb"), + [HSIO] = DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"), +}; + +const struct resource vsc7512_port_io_res[] = { + DEFINE_RES_REG_NAMED(VSC7512_PORT_0_RES_START, VSC7512_PORT_RES_SIZE, "port0"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_1_RES_START, VSC7512_PORT_RES_SIZE, "port1"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_2_RES_START, VSC7512_PORT_RES_SIZE, "port2"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_3_RES_START, VSC7512_PORT_RES_SIZE, "port3"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_4_RES_START, VSC7512_PORT_RES_SIZE, "port4"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_5_RES_START, VSC7512_PORT_RES_SIZE, "port5"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_6_RES_START, VSC7512_PORT_RES_SIZE, "port6"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_7_RES_START, VSC7512_PORT_RES_SIZE, "port7"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_8_RES_START, VSC7512_PORT_RES_SIZE, "port8"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_9_RES_START, VSC7512_PORT_RES_SIZE, "port9"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_10_RES_START, VSC7512_PORT_RES_SIZE, "port10"), + {} +}; + static const struct mfd_cell vsc7512_devs[] = { { .name = "ocelot-pinctrl", @@ -127,7 +194,7 @@ static const struct mfd_cell vsc7512_devs[] = { static void ocelot_core_try_add_regmap(struct device *dev, const struct resource *res) { - if (dev_get_regmap(dev, res->name)) + if (!res->start || dev_get_regmap(dev, res->name)) return; ocelot_spi_init_regmap(dev, res); @@ -144,6 +211,7 @@ static void ocelot_core_try_add_regmaps(struct device *dev, int ocelot_core_init(struct device *dev) { + const struct resource *port_res; int i, ndevs; ndevs = ARRAY_SIZE(vsc7512_devs); @@ -151,6 +219,16 @@ int ocelot_core_init(struct device *dev) for (i = 0; i < ndevs; i++) ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]); + /* + * Both the target_io_res and tbe port_io_res structs need to be referenced directly by + * the ocelot_ext driver, so they can't be attached to the dev directly + */ + for (i = 0; i < TARGET_MAX; i++) + ocelot_core_try_add_regmap(dev, &vsc7512_target_io_res[i]); + + for (port_res = vsc7512_port_io_res; port_res->start; port_res++) + ocelot_core_try_add_regmap(dev, port_res); + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL); } EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT); diff --git a/include/linux/mfd/ocelot.h b/include/linux/mfd/ocelot.h index dd72073d2d4f..439ff5256cf0 100644 --- a/include/linux/mfd/ocelot.h +++ b/include/linux/mfd/ocelot.h @@ -11,8 +11,13 @@ #include #include +#include + struct resource; +extern const struct resource vsc7512_target_io_res[TARGET_MAX]; +extern const struct resource vsc7512_port_io_res[]; + static inline struct regmap * ocelot_regmap_from_resource_optional(struct platform_device *pdev, unsigned int index,