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Miller" , Vladimir Oltean , Florian Fainelli , Vivien Didelot , Andrew Lunn , Krzysztof Kozlowski , Rob Herring , Lee Jones Subject: [RFC v4 net-next 17/17] mfd: ocelot: add external ocelot switch control Date: Sat, 8 Oct 2022 11:51:52 -0700 Message-Id: <20221008185152.2411007-18-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221008185152.2411007-1-colin.foster@in-advantage.com> References: <20221008185152.2411007-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR03CA0304.namprd03.prod.outlook.com (2603:10b6:303:dd::9) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWHPR1001MB2351:EE_|PH7PR10MB6506:EE_ X-MS-Office365-Filtering-Correlation-Id: cb37ee54-4735-41c9-04ce-08daa95e3617 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6aXf5tkYEfUxk4GvMt4Ta91qEfUpFLY//1vlQYoTuUtWWAAAzl0RdGj8KUk401b8Bmg5S7QW9grjieKEtF4N9XrT3W2C3PyNXm0mx9uN8TE2MNaYRvL7cfTzBQdlEybZeXYizsM5CSlylHr9rEe5lqBdNOoOAaJvRMh3XhyjrYKfqBexjU518ata2vVEAgoEBfPYVgIrEaCAerxIVJTXciztpEfvy6lSQREgxcO/vi6YyUlLI/6J/BJItgV6uBlzxnFVdXbNPp4VOCwoNYFspQqu/O/HY+TbVC6utKd1MoRk+hWjnhK2mbEJ7wbC0SVw0srtO7YqcH2kzVgEzTij99VBmWioLiB/v/nk7kxJTyfZafKIclSwCxD6Y0/14KddmSvPZGC1VDbWz+7G+q5YM0JAAjjGnfkhl8zurH5PHAAIezk394lCg0h/XOhnW8s3xK3RMaX3l7GeO78fzVDWykCNy+el2BXOTfunpopWYddclHVXXmtGcQsNdHCpKBwWjvOvnbz5yxOomGyyTO6woidxCPEMzE+MjpS8NQnNiJmisGF7KodWC0ZsxQ7nqo0cdLhNToaM82kNSProW0xsZDAq7Gvict/ECXx3MPj0L0J3T5NP/smZ80mMgK00mCyUsnRiva0VImg3er86KTTRKGa8fG9ErLMHwtqzIKupQMQidslKe11dYc33zGiUQzzJTQlJqF0NNT661GoYjUU9QKF9IfyPiDBsBHEe65zI//Fpo3IVaAx9SZvMTyyJvryL7vBURVSM7SmLQcs2cSbERw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(366004)(39840400004)(346002)(136003)(396003)(376002)(451199015)(26005)(41300700001)(6512007)(86362001)(1076003)(36756003)(2906002)(186003)(66946007)(66476007)(4326008)(66556008)(2616005)(6666004)(8676002)(6486002)(38350700002)(478600001)(54906003)(316002)(6506007)(52116002)(38100700002)(5660300002)(44832011)(7416002)(8936002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sjr42qKEc+jBc7gZd9D23XgRt5agneV7yJtW5jaD8Pv+8+neY0MXTabykVYFlb3DV0N3MYGshiaub+rItoozs2M6hZerre25eVEQIFOykIqKJgqUPYl/geOkDdwEey+ueRIy+jVGQRrD/cABr7b4QcJofFDQpNiNFUxRs6gwmI2jW5zvXiGMlZ37yz1EWFzfFsr+n/fd1V1FReaQDLX0Kfrjvv/Zs3rQwhTbya1eOZckVXIkTjC0AgNhVHLI7lSaGWqVWDDjkpSK1ThzgdQe+doU/vGPcGLY8yKAAxUhInJTnMv7CBHfMrUBOM7ssOLrM9LS2WFR04prU1mZVRi03MfDpwE+5zKhoBx22lCIKVwP3vwu4JEjNkW0m3TU06k7KI/mQWeinlNjdorPKpJX8opcZsnBn2WZWjTb0lp+krURwWSAx5mMNrBi5uVboLkiR+uBrFPYzzeay+0v/E4D66r0Oa8bTxMMKG3JcJFohrRgOEJFjgZ5eVtqLA5aGXeKwo0VKW/lXEVV8gVf3Wmn1kGJQgMLNmCCV1JQoBYzJoe1gCY1nLQjXo4VQJSyotxIGYsMeItGM/PgtV5CV/kC7m8p3fvcLMPprZ0lPxnyBZkSborypuY+tr6XKZN73f8qSiDjoBSQ/a0bEeIf711wXi1I0u5kLY4G43fkKs8uTaoaTM54ZfyoGjfZvMbVJ4GkkyAoM8mGJpy6m/F6DkVSfWCjShMydrnyiPfqjO0pG/95o+OFXnTWvQeppAxAvdP9m/HJNy5a485T1rAdlLl3jPCKVH6WG9PsGUjGY1DwXS4KncNkScqAgUO6f3K8/PNy1y7oyWFSo8RYSsnA9pFVwajOc2S332ITMSWM9CI69NlE+5VP8mLKTkds/dDVPm5iaSvYDeqXZtWom/yRemxyhDbUZw8MhZ6sAAjm3Y3Sd7Jd2yt9o6Q5kyFFZoWSu+GXHtptnvMeNAm7o/fG3bFih9wb6Oz4MV/vWAiXP6lD3gQpZfM+TT+jz0WGFuEDs8Qy5sbDgZ8yBfYNGWuNogKEz+bJ3ks/TsYfV9N3ZnI1WbxVt7STdAKG18y/EnE9ei/jeBOAxvOv2R2jL/bbYjC3uMELkqJpMlr1yGQwnFF+HUh4CmNU37r/ymAadeLIT8P2xxrnQXSGW3yFCQ8fzPKPtBXRVoqJJV5SpeFhyw7/4c2wdeU7GdJwG0Xa1kZ/k0hwUwzdr5psAyTBrzOxJjtGn2mGSy7obwJ4CkQfJuYfX9gXypY93fkfFhwWMnpC/k1ABMciW+BlbsUgnhguUl4gIEFkbf0AMjah5ceO4OwQKFpHqg+tBDbtbG4q3XW4n5gLEvsxgBvv1QjcdPcWQhL7M0o7Ufo25KScSDokWtlZuuZktTCk8kYJ19ut2gMuMwwIkJFPWRnvsTILJ1k6s9zaTN/9odLldj6XFD9kRcWKCwKCYRGqRLh1vsYscJgK3yqw/A/roLSrNmOqy1AAJ1J7qBdZDF/Q3GTO3gHD/WduGRV+4r0Tug0uPcB025zvZhE7e+Bdg2hogNQU/H5Nz3/aUTxGs/w57gW4/d1syUeR1mwvy1CIqCi1hqBdxfkmY1zwNNLnPHVQ71jGCcIO/o24YqQ/Qbw6+WhuV83++9ZEtNc= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: cb37ee54-4735-41c9-04ce-08daa95e3617 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2022 18:52:12.7250 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: POAsih8R0JdjLru4JnSQ2NUyADEqmRNMkFqzmGB4LOyGXinWfdbBCSPmcW90dNbjYfkUXMP4NEW1ONMC0l8y6Gk+fT8PcF5gJAKKPHqkPzU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR10MB6506 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Utilize the existing ocelot MFD interface to add switch functionality to the Microsemi VSC7512 chip. Signed-off-by: Colin Foster --- v4 * Integrate a different patch, so now this one - Adds the resources during this patch. Previouisly this was done in a separate patch - Utilize the standard {,num_}resources initializer v3 * No change v2 * New patch, broken out from a previous one --- drivers/mfd/ocelot-core.c | 60 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index 013e83173062..f35b4b2d4eec 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -45,6 +45,39 @@ #define VSC7512_SIO_CTRL_RES_START 0x710700f8 #define VSC7512_SIO_CTRL_RES_SIZE 0x00000100 +#define VSC7512_ANA_RES_START 0x71880000 +#define VSC7512_ANA_RES_SIZE 0x00010000 + +#define VSC7512_QS_RES_START 0x71080000 +#define VSC7512_QS_RES_SIZE 0x00000100 + +#define VSC7512_QSYS_RES_START 0x71800000 +#define VSC7512_QSYS_RES_SIZE 0x00200000 + +#define VSC7512_REW_RES_START 0x71030000 +#define VSC7512_REW_RES_SIZE 0x00010000 + +#define VSC7512_SYS_RES_START 0x71010000 +#define VSC7512_SYS_RES_SIZE 0x00010000 + +#define VSC7512_S0_RES_START 0x71040000 +#define VSC7512_S1_RES_START 0x71050000 +#define VSC7512_S2_RES_START 0x71060000 +#define VCAP_RES_SIZE 0x00000400 + +#define VSC7512_PORT_0_RES_START 0x711e0000 +#define VSC7512_PORT_1_RES_START 0x711f0000 +#define VSC7512_PORT_2_RES_START 0x71200000 +#define VSC7512_PORT_3_RES_START 0x71210000 +#define VSC7512_PORT_4_RES_START 0x71220000 +#define VSC7512_PORT_5_RES_START 0x71230000 +#define VSC7512_PORT_6_RES_START 0x71240000 +#define VSC7512_PORT_7_RES_START 0x71250000 +#define VSC7512_PORT_8_RES_START 0x71260000 +#define VSC7512_PORT_9_RES_START 0x71270000 +#define VSC7512_PORT_10_RES_START 0x71280000 +#define VSC7512_PORT_RES_SIZE 0x00010000 + #define VSC7512_GCB_RST_SLEEP_US 100 #define VSC7512_GCB_RST_TIMEOUT_US 100000 @@ -96,6 +129,28 @@ static const struct resource vsc7512_sgpio_resources[] = { DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"), }; +static const struct resource vsc7512_switch_resources[] = { + DEFINE_RES_REG_NAMED(VSC7512_ANA_RES_START, VSC7512_ANA_RES_SIZE, OCELOT_RES_NAME_ANA), + DEFINE_RES_REG_NAMED(VSC7512_QS_RES_START, VSC7512_QS_RES_SIZE, OCELOT_RES_NAME_QS), + DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, OCELOT_RES_NAME_QSYS), + DEFINE_RES_REG_NAMED(VSC7512_REW_RES_START, VSC7512_REW_RES_SIZE, OCELOT_RES_NAME_REW), + DEFINE_RES_REG_NAMED(VSC7512_SYS_RES_START, VSC7512_SYS_RES_SIZE, OCELOT_RES_NAME_SYS), + DEFINE_RES_REG_NAMED(VSC7512_S0_RES_START, VCAP_RES_SIZE, OCELOT_RES_NAME_S0), + DEFINE_RES_REG_NAMED(VSC7512_S1_RES_START, VCAP_RES_SIZE, OCELOT_RES_NAME_S1), + DEFINE_RES_REG_NAMED(VSC7512_S2_RES_START, VCAP_RES_SIZE, OCELOT_RES_NAME_S2), + DEFINE_RES_REG_NAMED(VSC7512_PORT_0_RES_START, VSC7512_PORT_RES_SIZE, "port0"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_1_RES_START, VSC7512_PORT_RES_SIZE, "port1"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_2_RES_START, VSC7512_PORT_RES_SIZE, "port2"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_3_RES_START, VSC7512_PORT_RES_SIZE, "port3"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_4_RES_START, VSC7512_PORT_RES_SIZE, "port4"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_5_RES_START, VSC7512_PORT_RES_SIZE, "port5"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_6_RES_START, VSC7512_PORT_RES_SIZE, "port6"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_7_RES_START, VSC7512_PORT_RES_SIZE, "port7"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_8_RES_START, VSC7512_PORT_RES_SIZE, "port8"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_9_RES_START, VSC7512_PORT_RES_SIZE, "port9"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_10_RES_START, VSC7512_PORT_RES_SIZE, "port10") +}; + static const struct mfd_cell vsc7512_devs[] = { { .name = "ocelot-pinctrl", @@ -121,6 +176,11 @@ static const struct mfd_cell vsc7512_devs[] = { .use_of_reg = true, .num_resources = ARRAY_SIZE(vsc7512_miim1_resources), .resources = vsc7512_miim1_resources, + }, { + .name = "ocelot-switch", + .of_compatible = "mscc,vsc7512-switch", + .num_resources = ARRAY_SIZE(vsc7512_switch_resources), + .resources = vsc7512_switch_resources, }, };