From patchwork Sat Oct 8 18:51:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 13001844 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1AE3C433FE for ; Sat, 8 Oct 2022 18:52:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229805AbiJHSwQ (ORCPT ); Sat, 8 Oct 2022 14:52:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229764AbiJHSwL (ORCPT ); Sat, 8 Oct 2022 14:52:11 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2118.outbound.protection.outlook.com [40.107.94.118]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A19A93F1DA; Sat, 8 Oct 2022 11:52:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=F20tlcYgvgXFrydMvrpff+o/fkHXSFA2hPJzszq4oiz59ldOQK8qSzMQ66ugwZAv4XejBecuLZr2tdtEW2jI5Vy+2bDTVHO+6aZ2koMSXMWdyMdwcm5jA92A0iGrXy+EuSa4RjonX9OB1tjBUXN2Fa/Y49lGYFpigVruerVoCvb8yOBG9S2r/GFfEQs2k2HR3sU1c8M/3Fr80g71GqvV5lt5bfjcPsA+P2LDy5UljKIVyyRo5MZJ+IiYWkpiVgwaXPHLZYgZ7yurgFRRnJGijLQOq2834uQ+Uy+g+ez3pwQvve0e2QH0sdutr4B/BMcNyNRF0nspny9n9gxruQ9xew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9WMNRm7MJre1ZENaAT9rfjXZ7N/EsBrIby4woWSQ8hQ=; b=dDS2E1NvVM9My7PI52u2aTtKi1eJ2Z3JgpWlsjoSXZeUdSta1TYdogW4bp34dX1K+lWEBUEJmXyd3sMyKcUSPqVoPAEQyusOCwvJ4bjUcGzXKLVEeihm9OChQYJHhMK8G5iucZgTpaf0Ue4oBzvmUDjQQRkLl2LcDebyMTuehq9xuKBfKX8OoWztXI/2GDx0W9n7TF87NE+F08RSH6V5MfozCerLniJU2v/yLTel8T0FVLM6Icpm+V5ggG6GrsZ8PmpBaq5Ak5M4YhDwjrHS4tYdC75PdyhLdPqcuBIjKOsPqCaX0XixNPo/VjDBfxEKtM4suQeyWt85dwGMcfTrtQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9WMNRm7MJre1ZENaAT9rfjXZ7N/EsBrIby4woWSQ8hQ=; b=ifzc+RoBnyxt/rF2/X6F2pJwza0sScaG7O0CLJOMTUbkE3tF6VUeds4jYh+LX0vkzqbcXpqkTuhcJJW7hd1nMluHVOy+AiuKCmgW9WQwMwlZ17093cyQt+qbBeYcKofmGwh4hb1JukOMetE/ei/9mRhUwe8Pm/6l3Zd3rI5MThY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by PH7PR10MB6129.namprd10.prod.outlook.com (2603:10b6:510:1f7::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.20; Sat, 8 Oct 2022 18:52:05 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::ee5e:cbf9:e304:942f]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::ee5e:cbf9:e304:942f%7]) with mapi id 15.20.5676.028; Sat, 8 Oct 2022 18:52:05 +0000 From: Colin Foster To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Russell King , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. Miller" , Vladimir Oltean , Florian Fainelli , Vivien Didelot , Andrew Lunn , Krzysztof Kozlowski , Rob Herring , Lee Jones , Vladimir Oltean Subject: [RFC v4 net-next 02/17] net: mscc: ocelot: expose regfield definition to be used by other drivers Date: Sat, 8 Oct 2022 11:51:37 -0700 Message-Id: <20221008185152.2411007-3-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221008185152.2411007-1-colin.foster@in-advantage.com> References: <20221008185152.2411007-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR03CA0304.namprd03.prod.outlook.com (2603:10b6:303:dd::9) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWHPR1001MB2351:EE_|PH7PR10MB6129:EE_ X-MS-Office365-Filtering-Correlation-Id: b794e887-3c48-4a40-03fa-08daa95e3150 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sZ1XBsB2apiXIq3yLLF/VFzZsCKeueiqFrJI0U0SS9/b8KZ5QnBww/hnGkHToB5nCimgW+lpBN9zXCof2Nu6DFFMHKxqz76+5twmLDEd+8jWFGQGo83SQUGTHIRJ62KVGdYQ/7+WgLtTOIQuQDCgtSETRp9BvYZF1QFGQtEq0Jhu2Os16TPEoQirGKiZRrC+bnb32RGIFcyJOylF0FQ9pGerKpBxLpgJ4qQx2fObQ/qg7MJT1O47CkdcJGzOfU6rTWRXAnJjFbofLhHvSdVtk3+sJNyNc7q5n8eWrN93L1MRXH7We/pxTg8aEeyPo6Hb6qHUyl38fEwJvOxItgvalb4XypPrNZxlR8Om8297As29g92EZSFGuwhSSYwnqZKlhwtlGlyYlhquxq0oyAqANu2kykIcEJBYr+T3h+Leeh9nOx1uccYCXI6UuFqw/JkqRghEokmvLXW+kjnvfTYHiPfN4iI8sB+fEqB9OrvfMqPU6tWv4bFaC6RNRoJmWVO0kzXQv8u4VFnZp05XLp/a+LniJXyyhKJGFbpsULcC7eS9BfpwxgCEig2WNcRiHZbxMO8vAlWia6OBxGvymiieqqh4xE+YL/or3rHo8GKoBp0aqeAszcgpL7N6/ra05IUWEazmmw1uRJXiL0JxXhXiPYEPRmSP8AM50o33uj0B2elbwn1umAs20dpNZnPN/1NEFciy6Ch6QIuUc2GqryVBhFxZm7DSUMZjlTwMLrolqtBogVcGJ2bx2kNEisOfqhTQ X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(346002)(39830400003)(376002)(366004)(136003)(396003)(451199015)(44832011)(186003)(6512007)(6666004)(26005)(6486002)(6506007)(30864003)(2616005)(316002)(54906003)(38100700002)(38350700002)(52116002)(4326008)(86362001)(83380400001)(1076003)(478600001)(36756003)(7416002)(2906002)(41300700001)(8676002)(66476007)(8936002)(5660300002)(66946007)(66556008);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UqAMpe/9sj3iuJtyiqOGkH+fPeh4a+Ho6Dv5wt4ztOQxTwWQj8eKVxkda3brW21QqX1Kx0+IVU79wcjh5AW83SUtpfrExvc+LW1vCO1ULdoDMxCWCGUCNI1jOsOFrSGCnQwiC5RmPe7+xvvRXm2Fs0rTPZ6IFuurfrcAf4+bC0Y8JIFCHKctN+yrszyB9SABpPyKNePIjg0OxP3pyKxAmRCHd7Pyh+PLhJCCFwJXx1Qxcy/DE996RMwej/0+iR29LPeSNn2L+VsuE2+i9+LhLXIO74t8Wmojr1afZ2JJBLxkZI3n9kHS98VNZ3Z0yFTKJfysWj9F8nxSoBAxpHjRqIzJ0Jk8oskZdKKqwHX/y5fRfat1/M7kjzrsrxjLeR4XC3EKk2ti7azeVNA6GRNyNy6i054BF+s3uFv57EuXPvtIYs1Ru1qOBf3RcKgp5+hMursg2MD9wF9ToA6GJzt26JkycYIqAdWst59fJBvtD5hqgB9e6kogr/ygHD8tz2O8wNbm6SCEWlICcJYnBSoRd3EtPX3B9VdyJ/3Jl+jek19FH0Gd5dDG/FM4osIx+wYm6yxbzg1uPfL7Fs/VNci0XgL03Mc55zW+E43OFx5HQy9SZMzNxtJGZmTzWob2q2h4+/Gsl895uInoPt4iKASGe4D+ro8bstJBlTTa0nx8P1Fy/I5EdakXEHd42rZCdDw+foMGytKb8wbacQ0oUl/3hiivQz6fO7SB8EBBSsTictFachiA9oN+Cnpj1J9QA6hoepcTBTMch5q27cl5K7pwyVDExcE17FRrzqFyKZscOuPgASgi1qczWFxF+FHKSpAsw9lzzr3ltraZ/k8GYJ5y7U5IBxnG/AiwCCWyOXSv/t3N3iHFNmC7icshkNgxoe6dQXIekEU+MVfrpdCB6VtVSGCOL09zLknT1aGl2Ha5mmsUd13bvglwEnRRTZhkdsrJ5mUzCzBucsMsXoqL1Sv0Q/Gwjpxa+6izMP7pA9KnJOCjGsZS60PZ6yxlqJJq0PkO8RuwiXZsVFAjpjVF5tDCgfdqIeV1oZpyxurARKsTqptjRMHrLhSipQy9mhzt2fvWLJu6DioYhXgUqFL+clvP3El3RMqc4fauKSwH43Tm/c7siuqLemlITm1ICMyLc8TqE1Y7yWAzvf/Mi6E8OfMQmVs1UkLlpfdj0uZOKb7CTXHOoKMYk90vMHC1UXMYCx1biKaI3nNfNwAva9p74xdMwk5E4T5A0FwQhFVTjuDqdwqqVPu7rc9JpYEk/fTqlE2KubOirj6wXfVylBdYFiDnLBdWexb+NPval6O3TNx8cVV4lFJUQezeCylu/y+vbEIO9UIlX30QcWBXCCOroHpq/gY1yjo4BgtP8z9YRof5TTjYH+UZ+QjyHCl/680fptPc17rBXWJS1uMGHnQcPGJBRLoi6o6s1+VsfcZWbrT1ITrSwDhLzg9YT7Y0Jy7Y5Qs+MzRK4YBfHs9ZVXLuKoEqFbB1YTMf+WU6unJADBDwOEmPkKvRMK5pNYmpk1Om0ivuNYAeOd34Bl+yheLF/c3Hz4PWRFvsHqyrPsxtCwZ2LXrscz5jeK9/uH18kpR8rQVoANTs2PFDNnX0jpfkii/LSg== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: b794e887-3c48-4a40-03fa-08daa95e3150 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2022 18:52:04.7256 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6ePm5eOUDRjb+4tEXUX4lpM4qWY0qMG+fc1YlIPf8isq81i5rRFe+gVeqlmMGjnTiDmnPWvDGI8uGyhxY+CAQDLRZAhUYT8c/rSFrzTe9r8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR10MB6129 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The ocelot_regfields struct is common between several different chips, some of which can only be controlled externally. Export this structure so it doesn't have to be duplicated in these other drivers. Rename the structure as well, to follow the conventions of other shared resources. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean --- v3-v4 * No changes v2 * Add Reviewed tag v1 from previous RFC: * Remove GCB_SOFT_RST_SWC_RST entry from the regfields struct - it isn't used. * Export the vsc7514_regfields symbol so it can be used as a module. --- drivers/net/ethernet/mscc/ocelot_vsc7514.c | 60 +--------------------- drivers/net/ethernet/mscc/vsc7514_regs.c | 59 +++++++++++++++++++++ include/soc/mscc/vsc7514_regs.h | 2 + 3 files changed, 62 insertions(+), 59 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index bac0ee9126f8..6d695375b14b 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -42,64 +42,6 @@ static const u32 *ocelot_regmap[TARGET_MAX] = { [DEV_GMII] = vsc7514_dev_gmii_regmap, }; -static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { - [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), - [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), - [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), - [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), - [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), - [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), - [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), - [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), - [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), - [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), - [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), - [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), - [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), - [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), - [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), - [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), - [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), - [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), - [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), - [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), - [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), - [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), - [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), - [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), - [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), - [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), - [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), - [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), - [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), - [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), - [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), - [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), - [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), - [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), - [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), - [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), - [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), - [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), - [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), - [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), - [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), - /* Replicated per number of ports (12), register size 4 per port */ - [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), - [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), - [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), - [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), - [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), - [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), - [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), - [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), - [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), - [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), - [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), - [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), - [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), -}; - static const struct ocelot_stat_layout ocelot_stats_layout[OCELOT_NUM_STATS] = { OCELOT_COMMON_STATS, }; @@ -142,7 +84,7 @@ static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) ocelot->num_mact_rows = 1024; ocelot->ops = ops; - ret = ocelot_regfields_init(ocelot, ocelot_regfields); + ret = ocelot_regfields_init(ocelot, vsc7514_regfields); if (ret) return ret; diff --git a/drivers/net/ethernet/mscc/vsc7514_regs.c b/drivers/net/ethernet/mscc/vsc7514_regs.c index 9d2d3e13cacf..123175618251 100644 --- a/drivers/net/ethernet/mscc/vsc7514_regs.c +++ b/drivers/net/ethernet/mscc/vsc7514_regs.c @@ -9,6 +9,65 @@ #include #include "ocelot.h" +const struct reg_field vsc7514_regfields[REGFIELD_MAX] = { + [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), + [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), + [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), + [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), + [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), + [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), + [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), + [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), + [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), + [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), + [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), + [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), + [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), + [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), + [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), + [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), + [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), + [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), + [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), + [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), + [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), + [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), + [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), + [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), + [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), + [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), + [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), + [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), + [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), + [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), + [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), + [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), + [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), + [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), + [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), + [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), + [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), + [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), + [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), + [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), + [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), + /* Replicated per number of ports (12), register size 4 per port */ + [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), + [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), + [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), + [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), + [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), + [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), + [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), + [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), + [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), + [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), + [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), + [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), + [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), +}; +EXPORT_SYMBOL(vsc7514_regfields); + const u32 vsc7514_ana_regmap[] = { REG(ANA_ADVLEARN, 0x009000), REG(ANA_VLANMASK, 0x009004), diff --git a/include/soc/mscc/vsc7514_regs.h b/include/soc/mscc/vsc7514_regs.h index ceee26c96959..9b40e7d00ec5 100644 --- a/include/soc/mscc/vsc7514_regs.h +++ b/include/soc/mscc/vsc7514_regs.h @@ -10,6 +10,8 @@ #include +extern const struct reg_field vsc7514_regfields[REGFIELD_MAX]; + extern const u32 vsc7514_ana_regmap[]; extern const u32 vsc7514_qs_regmap[]; extern const u32 vsc7514_qsys_regmap[];