| Message ID | 20221014064735.18928-1-harini.katakam@amd.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 0c9efbd5c50c64ead434960a404c9c9a097b0403 |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [v2] net: phy: dp83867: Extend RX strap quirk for SGMII mode | expand |
On Fri, Oct 14, 2022 at 12:17:35PM +0530, Harini Katakam wrote: > When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4 > register should be set. The former is already handled in > dp83867_config_init; add the latter in SGMII specific initialization. > > Fixes: 2a10154abcb7 ("net: phy: dp83867: Add TI dp83867 phy") > Signed-off-by: Harini Katakam <harini.katakam@amd.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Please see the netdev FAQ. You are supposed to put the tree this patch is for in the subject line, [PATCH net v2] ... etc. Please remember this for next time. Andrew
Hello: This patch was applied to netdev/net.git (master) by David S. Miller <davem@davemloft.net>: On Fri, 14 Oct 2022 12:17:35 +0530 you wrote: > When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4 > register should be set. The former is already handled in > dp83867_config_init; add the latter in SGMII specific initialization. > > Fixes: 2a10154abcb7 ("net: phy: dp83867: Add TI dp83867 phy") > Signed-off-by: Harini Katakam <harini.katakam@amd.com> > > [...] Here is the summary with links: - [v2] net: phy: dp83867: Extend RX strap quirk for SGMII mode https://git.kernel.org/netdev/net/c/0c9efbd5c50c You are awesome, thank you!
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 6939563d3b7c..417527f8bbf5 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -853,6 +853,14 @@ static int dp83867_config_init(struct phy_device *phydev) else val &= ~DP83867_SGMII_TYPE; phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); + + /* This is a SW workaround for link instability if RX_CTRL is + * not strapped to mode 3 or 4 in HW. This is required for SGMII + * in addition to clearing bit 7, handled above. + */ + if (dp83867->rxctrl_strap_quirk) + phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, + BIT(8)); } val = phy_read(phydev, DP83867_CFG3);
When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4 register should be set. The former is already handled in dp83867_config_init; add the latter in SGMII specific initialization. Fixes: 2a10154abcb7 ("net: phy: dp83867: Add TI dp83867 phy") Signed-off-by: Harini Katakam <harini.katakam@amd.com> --- drivers/net/phy/dp83867.c | 8 ++++++++ 1 file changed, 8 insertions(+)