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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Richard Cochran , Rahul Rameshbabu , Jacob Keller , Aya Levin , Gal Pressman Cc: netdev@vger.kernel.org Subject: [PATCH net-next 2/2] net/mlx5: Implement ptp_clock_info .getfine function Date: Fri, 2 Dec 2022 12:15:31 -0800 Message-Id: <20221202201528.26634-3-rrameshbabu@nvidia.com> X-Mailer: git-send-email 2.36.2 In-Reply-To: <20221202201528.26634-1-rrameshbabu@nvidia.com> References: <20221202201528.26634-1-rrameshbabu@nvidia.com> X-ClientProxiedBy: BYAPR08CA0038.namprd08.prod.outlook.com (2603:10b6:a03:117::15) To BYAPR12MB2743.namprd12.prod.outlook.com (2603:10b6:a03:61::28) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR12MB2743:EE_|PH7PR12MB7308:EE_ X-MS-Office365-Filtering-Correlation-Id: ef19b397-e2d9-439d-2593-08dad4a215bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Q4LadLdaUhXWFlw9BDUU4xAy5YXt3PJpBoxqXpQwUbXnrHUr/Ai2Boss9UvKDHShaV2hnkOQp7/70CLKQoAWpMj14lC2N/B6blilawoMfk2X2ft0vfzhpH/hcOonS1lgb94VLvaAn2eSuNvSIRr+VBb71KDeKvjFEYJY7Fd1HfYIm6nvnyRO0BXMN3hpRyGFkKrVNdI8UP5qwQKaGNppg3IybzADExN1Cnpg0NiUCveZRSP1BYFPz0378mJO5dR5XjddwjFMVXc60ZWC3ReuNCcwhLYM++3xX+aAcnB6zdnX8CW0X+gvmJ5RzXy728YlOBf3TyRdW6uwH9Psca+tBDzLBwYA5gIhgJbVHxneJ99JK7ixWIfCX7R9zUyjgZHM10LtCRaqz5at327f4ngNkGKzif6ZbH2xc90STznY0GRPUnvj4ve3Avv09a7yNR/OURlm58wC8U6Bz9HSrycdTjQpxrh4XhaCx7AGVovZWSYRSlJP5AMk1yQopewjr3xYz577DOE8jZmwvVLhwxytqgvbFsLzYjb+XozjVNwhOwk4g2JCyEgBXsnWhVLm215QMZoPSkJSMogDysUKA9ekUEI+n51B2JUcgts0/x8lU8jshE+44HrXjPqdDXzePhNYT7M8rAPXi1qQ8WSvc3q2f2q/zUmRLc1qDPPlxTJYU7c0zcm/KSTX5hW8c2ujKvXICcdttJW8TI1te1b7we3ftg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BYAPR12MB2743.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(39860400002)(136003)(376002)(366004)(451199015)(1076003)(2616005)(921005)(6636002)(6486002)(316002)(110136005)(36756003)(86362001)(5660300002)(6506007)(6666004)(38100700002)(83380400001)(186003)(6512007)(2906002)(8936002)(478600001)(66476007)(66556008)(66946007)(41300700001)(8676002)(4326008)(142923001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Dc1zYTFlJFTEs7lJCK8oYqDCyIUg6JCiTEg0KACjF40Lmht1yy4t+zT6SquclLYkydPDxpHhJXvR8Pk3S2f0zmz5kyVr3XgMeK/HNNt4lwbcZrLe2bazVFeAo1XBzam4ggV/rhyczT4tjvuUNbchMaAmjGZyKzRot2hIpsPSnrjbkf7xLsXasxIQzZ62GUgUqCwO2zXFRTTOly4w+0cIO4KVEdfdi4mCBm3N60uajBQfmNma0u83KeAYR8IF7dINqfnq5/lJEsflhXwOubpgqaT4aqeLwAew7Y3L/pEawj0ywgq3/a0UNWQL5BtZRJ8RVoKq6q3kmDSt0TJsd3fDov4Qtnzqobbd/HPB4u+Ee2+wP8ValifftKScxwwDygmqUR9SfXdZrIf+uNbBQqXOMW3PzaXBjHl5ZaPnAQjhUWhbT3nNbzokY5qbAtYqOmFbuUdUeEGHtAavgfQnVlUUJGVsDADmabBs3RcU74w6nh+ZGjm0dwYjrhB+IVprIb0JErlfImqmcofP1kqXT075XW5PXHyf7SNo63xW2NAXvWUi1e5RGV+1i+V3OtSso12nUCunbCUlkkSpzcXBiFtBgBdmd5XMt3yDWkkah15dvRl20Fq5ltc0osDjh40JTUerxRyQ2iakVSOgbDqrgLIlY0sx0bVNTbC6vBrcPaxz09A1ydHIfzTf3URkT8fUp+sJI7IeRDnb4yoKhMr5rX/SZg41r2E+vV/iCy5Hf9nlOeLHnKG2kYnf+iG0hPrpnv5YmAVygrBNsznoPCJapNA2sTu9DpbYsCt1G9pxkmA7nc+xiiWgdSd5hPyZlNuQJy1qOrdnrnNiSNB6Zjmr1bmkHuvvOUj9d6NGfqocnFgzc8jglv95FmymktvBb29DrW9am9GfykTkxAYAz4ObI5dX1AsFnNFseY41ED/Dsi0eIemAnxtwXecbG2m1ZJYxy3eiku8sHYqUyHk7yDGGsVdspDvl4aa00XvHjB0+XNxaBnpPm1s8WJWgb/UREL063EbPIiRgEPv4XQ+JDHQZlFPne1GfdKYgeDC/93znVmknHHaqsJaV0wH6Kle4+nG8zopzwsPPdC+vwC0uYeKvMIAmHrm5h65i6nq1cC2UEbC8RPraFyKNATtSks9BsakA1K7TrZRtkbjzyvGvXEOB2E3c5b56vi7U3KwDC3BHJLFInsi4L6KGRNoqAm/g9va2zLjWaVJ/PZSoFQ6euhLWRZQcdAtz63huHPRvxUyUfTJkVe/H5Wkda5H4UCTJiKXVc1cOlbxdeypggeIAiR1NplmQJeYPEYLuqJVn9BiNPmYrRqFn9lcpbrLizixV41t8YhiUkmFyJV67tZgHOoIPLNN/HgjSOYwe0ciXd6cR1VPQexJGSY3znFTFjjzN+XI1TyxPeciXtRofMB8HQJfGHyRkVRZIDKP4aTzjAGKJmye11b3W3P9+sf4jRgz2K1Y1o6itii4vXYYW86NUXLye0wQQCrNofsyZ05gSYwt8jwdACoGIrOmveZzRipVTzsqgjQ18RmHC3SXf6uxybRww5h4FzFXKpcRPEfyRJioIWAY9++YRK/pA0cp1QerwjgdTR6/JXfhfs/gB70XSe9BRDdXMkZefUzbC9yTdFvdOyASkTzxyjunJ0g6LHbh4cq7jts9qFiQWX13ckTCQfTC+POtRXg== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef19b397-e2d9-439d-2593-08dad4a215bb X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB2743.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 20:16:24.2129 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oYvg2BYRoiF+MIN/XtstzxeOiFmQfuGr6wW5BcEIzJ3Cp9Mdx5R5reyc3GaTuEhah5a1Vx3HMJcvnYk/Ne6zZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7308 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org .getfine gives the driver the ability to report the frequency offset from the device. The frequency offset from the nominal frequency is reported by the driver in scaled 16-bit fractional parts-per-million. Signed-off-by: Rahul Rameshbabu Reviewed-by: Gal Pressman Acked-by: Saeed Mahameed --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 69cfe60c558a..4ecf67f617c0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -326,6 +326,40 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) return 0; } +static int mlx5_ptp_getfine(struct ptp_clock_info *ptp, long *scaled_ppm) +{ + struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); + u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {}; + u32 out[MLX5_ST_SZ_DW(mtutc_reg)]; + struct mlx5_core_dev *mdev; + s64 delta; + int err; + + mdev = container_of(clock, struct mlx5_core_dev, clock); + + err = mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), + MLX5_REG_MTUTC, 0, 0); + if (err) + return err; + + delta = MLX5_GET(mtutc_reg, out, freq_adjustment); + /* Convert parts-per-billion (10^-9) to parts-per-million (10^-6) + * with a 16 bit binary fractional field + * + * scaled_ppm = ppb * 2^16 / 1000 + * + * which is equivalent to + * + * scaled_ppm = ppb * 2^13 / 125 + */ + delta <<= 13; + delta /= 125; + + *scaled_ppm = delta; + + return 0; +} + static int mlx5_ptp_adjfreq_real_time(struct mlx5_core_dev *mdev, s32 freq) { u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {}; @@ -688,6 +722,7 @@ static const struct ptp_clock_info mlx5_ptp_clock_info = { .n_pins = 0, .pps = 0, .adjfine = mlx5_ptp_adjfine, + .getfine = mlx5_ptp_getfine, .adjtime = mlx5_ptp_adjtime, .gettimex64 = mlx5_ptp_gettimex, .settime64 = mlx5_ptp_settime,