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[23.118.233.243]) by smtp.gmail.com with ESMTPSA id n4-20020a056870880400b0014866eb34cesm4979617oam.48.2023.02.06.21.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 21:28:36 -0800 (PST) From: Steev Klimaszewski To: Steev Klimaszewski Cc: Bjorn Andersson , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Marcel Holtmann , Johan Hedberg , Luiz Augusto von Dentz , Sven Peter , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-bluetooth@vger.kernel.org, Mark Pearson , Brian Masney Subject: [PATCH v4 3/4] arm64: dts: qcom: sc8280xp: Define uart2 Date: Mon, 6 Feb 2023 23:28:28 -0600 Message-Id: <20230207052829.3996-4-steev@kali.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230207052829.3996-1-steev@kali.org> References: <20230207052829.3996-1-steev@kali.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Steev Klimaszewski Reviewed-by: Brian Masney Reviewed-by: Konrad Dybcio --- Changes since v3: * Fix commit message changelog Changes since v2: * No changes since v2 Changes since v1: * change subject line, move node, and add my s-o-b --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index fa2d0d7d1367..eab54aab3b76 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1207,6 +1207,20 @@ spi2: spi@988000 { status = "disabled"; }; + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00988000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + operating-points-v2 = <&qup_opp_table_100mhz>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0098c000 0 0x4000>;