From patchwork Thu Mar 30 08:34:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13193595 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBCA4C77B6E for ; Thu, 30 Mar 2023 08:34:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229682AbjC3IeL (ORCPT ); Thu, 30 Mar 2023 04:34:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229710AbjC3Idt (ORCPT ); Thu, 30 Mar 2023 04:33:49 -0400 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1120B3; Thu, 30 Mar 2023 01:33:46 -0700 (PDT) Received: (Authenticated sender: clement.leger@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 42666C0009; Thu, 30 Mar 2023 08:33:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1680165225; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WwAhyV1Sj5KBBfVDCAdRTQpNDnZo2GvHv0Rky3dXMiQ=; b=FvKfGfSZ6CE043eolJcSg7z6fIgqiQ5Fle3qnqfqGZ8Jy2NG2lvc0m9kRNOiabUtHmpz+I qVQO7iL5hQgf5eLue/mh36wbIRDyD5+fSG9qDLr6FOKTkd4jgcjVor+XbxH1M14b2sBo+Z E/nbVZ/vi64gxVcGvKXKRKBhyGeQEZNlmHZCvGvPVmwYlPVaCzPC7iFsvNIyOpPtu8LdWU T+HCrZiRdahsgfyHNtPy5oPLTNRfh3Eww2CsZFbai2IiqyYxVb3oZicR6Aa1+s6tvd9MXp UrwsWF/IP5nAcw14KGSqaa0MIOrxhdXdF9JALgijw/w2dTh8J5psh/VqiYpxWw== From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Herve Codina , =?utf-8?q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , =?utf-8?q?Alexis_Lothor=C3=A9?= Subject: [PATCH net-next 2/2] net: dsa: rzn1-a5psw: disable learning for standalone ports Date: Thu, 30 Mar 2023 10:34:08 +0200 Message-Id: <20230330083408.63136-3-clement.leger@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230330083408.63136-1-clement.leger@bootlin.com> References: <20230330083408.63136-1-clement.leger@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org When port are in standalone mode, they should have learning disabled to avoid adding new entries in the MAC lookup table which might be used by other bridge ports to forward packets. While adding that, also make sure learning is enabled for CPU port. Signed-off-by: Clément Léger --- drivers/net/dsa/rzn1_a5psw.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c index bbc1424ed416..3e5062ab0928 100644 --- a/drivers/net/dsa/rzn1_a5psw.c +++ b/drivers/net/dsa/rzn1_a5psw.c @@ -336,6 +336,14 @@ static void a5psw_flooding_set_resolution(struct a5psw *a5psw, int port, a5psw_reg_writel(a5psw, offsets[i], a5psw->bridged_ports); } +static void a5psw_port_set_standalone(struct a5psw *a5psw, int port, + bool standalone) +{ + a5psw_port_learning_set(a5psw, port, !standalone, false); + a5psw_flooding_set_resolution(a5psw, port, !standalone); + a5psw_port_mgmtfwd_set(a5psw, port, standalone); +} + static int a5psw_port_bridge_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, bool *tx_fwd_offload, @@ -351,8 +359,7 @@ static int a5psw_port_bridge_join(struct dsa_switch *ds, int port, } a5psw->br_dev = bridge.dev; - a5psw_flooding_set_resolution(a5psw, port, true); - a5psw_port_mgmtfwd_set(a5psw, port, false); + a5psw_port_set_standalone(a5psw, port, false); return 0; } @@ -362,8 +369,7 @@ static void a5psw_port_bridge_leave(struct dsa_switch *ds, int port, { struct a5psw *a5psw = ds->priv; - a5psw_flooding_set_resolution(a5psw, port, false); - a5psw_port_mgmtfwd_set(a5psw, port, true); + a5psw_port_set_standalone(a5psw, port, true); /* No more ports bridged */ if (a5psw->bridged_ports == BIT(A5PSW_CPU_PORT)) @@ -755,13 +761,15 @@ static int a5psw_setup(struct dsa_switch *ds) if (dsa_port_is_unused(dp)) continue; - /* Enable egress flooding for CPU port */ - if (dsa_port_is_cpu(dp)) + /* Enable egress flooding and learning for CPU port */ + if (dsa_port_is_cpu(dp)) { a5psw_flooding_set_resolution(a5psw, port, true); + a5psw_port_learning_set(a5psw, port, true, false); + } - /* Enable management forward only for user ports */ + /* Enable standalone mode for user ports */ if (dsa_port_is_user(dp)) - a5psw_port_mgmtfwd_set(a5psw, port, true); + a5psw_port_set_standalone(a5psw, port, true); } return 0;