From patchwork Fri Apr 7 12:23:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Krishna Gajula X-Patchwork-Id: 13204722 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E84C3C77B61 for ; Fri, 7 Apr 2023 12:24:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240739AbjDGMYR (ORCPT ); Fri, 7 Apr 2023 08:24:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240716AbjDGMYM (ORCPT ); Fri, 7 Apr 2023 08:24:12 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80402A271; Fri, 7 Apr 2023 05:24:11 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 337AxF3r000893; Fri, 7 Apr 2023 05:24:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2eugfjHN5cEXVXyZBKU/nW9nBVOQy0d2Nhqol6lbOzo=; b=WG7PKm3bN8Pr7monF/nR62TmsxjNvF5hVLMYpqwBbhbyRIORIy3NnOIIwGTRnNjf7b+V hhP3L1CAHdhcqGMpKLEempefWfse2XWPbPY/aC7x/k8CpdhO2RS0hiTk/SET/eguzEq4 3TCy8/NmU2gpsAWMkkVBpAra5+lOjt7Rbo/bJh/ZcNtYgA+WLlu5yAC6n05pxDRmvwjX LkXOtHJkX34n0L2XIfelBSdttCgntN1Jp/lQW7dB3Ik5XF/qLmj8nNz3ToKiKlOhE6tv tuuEdXQPBz6WPFH60LQHexeyKUa2X0e59SJwENsESXGlaPnZjqCPymAmfDlBsdtSRKP5 3g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pthvw88py-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 07 Apr 2023 05:24:04 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 7 Apr 2023 05:24:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 7 Apr 2023 05:24:02 -0700 Received: from hyd1425.marvell.com (unknown [10.29.37.83]) by maili.marvell.com (Postfix) with ESMTP id E3F193F7060; Fri, 7 Apr 2023 05:23:57 -0700 (PDT) From: Sai Krishna To: , , , , , , , , , , , , CC: Ratheesh Kannoth , Sai Krishna Subject: [net PATCH v2 2/7] octeontx2-af: Fix start and end bit for scan config Date: Fri, 7 Apr 2023 17:53:39 +0530 Message-ID: <20230407122344.4059-3-saikrishnag@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230407122344.4059-1-saikrishnag@marvell.com> References: <20230407122344.4059-1-saikrishnag@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: pFsX-kAJYIi8LJyIrF0TvlW4pPOM3P8Y X-Proofpoint-GUID: pFsX-kAJYIi8LJyIrF0TvlW4pPOM3P8Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-07_08,2023-04-06_03,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Ratheesh Kannoth Fix the NPC nibble start and end positions in the bit map. Fix the depth of cam and mem table configuration. Increased the field size of dmac filter flows as cn10kb support large in number. Fixes: b747923afff8 ("octeontx2-af: Exact match support") Signed-off-by: Ratheesh Kannoth Signed-off-by: Sunil Kovvuri Goutham Signed-off-by: Sai Krishna --- drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c | 5 ++--- drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c | 4 ++-- drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h | 4 ++-- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index 006beb5cf98d..27603078689a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -593,9 +593,8 @@ static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf) * exact match code. */ masked_cfg = cfg & NPC_EXACT_NIBBLE; - bitnr = NPC_EXACT_NIBBLE_START; - for_each_set_bit_from(bitnr, (unsigned long *)&masked_cfg, - NPC_EXACT_NIBBLE_START) { + bitnr = NPC_EXACT_NIBBLE_START - 1; + for_each_set_bit_from(bitnr, (unsigned long *)&masked_cfg, NPC_EXACT_NIBBLE_END + 1) { npc_scan_exact_result(mcam, bitnr, key_nibble, intf); key_nibble++; } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c index 20ebb9c95c73..6597af84aa36 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_hash.c @@ -1868,9 +1868,9 @@ int rvu_npc_exact_init(struct rvu *rvu) rvu->hw->table = table; /* Read table size, ways and depth */ - table->mem_table.depth = FIELD_GET(GENMASK_ULL(31, 24), npc_const3); table->mem_table.ways = FIELD_GET(GENMASK_ULL(19, 16), npc_const3); - table->cam_table.depth = FIELD_GET(GENMASK_ULL(15, 0), npc_const3); + table->mem_table.depth = FIELD_GET(GENMASK_ULL(15, 0), npc_const3); + table->cam_table.depth = FIELD_GET(GENMASK_ULL(31, 24), npc_const3); dev_dbg(rvu->dev, "%s: NPC exact match 4way_2k table(ways=%d, depth=%d)\n", __func__, table->mem_table.ways, table->cam_table.depth); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 3d22cc6a2804..99cdc871b59c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -335,11 +335,11 @@ struct otx2_flow_config { #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ #define OTX2_VF_VLAN_RX_INDEX 0 #define OTX2_VF_VLAN_TX_INDEX 1 - u16 max_flows; - u8 dmacflt_max_flows; u32 *bmap_to_dmacindex; unsigned long *dmacflt_bmap; struct list_head flow_list; + u32 dmacflt_max_flows; + u16 max_flows; }; struct otx2_tc_info {