| Message ID | 20230511170202.742087-2-alexis.lothore@bootlin.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: dsa: rzn1-a5psw: disabled learning for standalone ports and fix STP support | expand |
On Thu, May 11, 2023 at 07:02:00PM +0200, alexis.lothore@bootlin.com wrote: > From: Clément Léger <clement.leger@bootlin.com> > > Currently, management frame were discarded before reaching the CPU port due > to a misconfiguration of the MGMT_CONFIG register. Enable them by setting > the correct value in this register in order to correctly receive management > frame and handle STP. > > Fixes: 888cdb892b61 ("net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver") > Signed-off-by: Clément Léger <clement.leger@bootlin.com> > Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com> > --- Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Hi,
kernel test robot noticed the following build errors:
[auto build test ERROR on net/main]
url: https://github.com/intel-lab-lkp/linux/commits/alexis-lothore-bootlin-com/net-dsa-rzn1-a5psw-enable-management-frames-for-CPU-port/20230512-010530
base: net/main
patch link: https://lore.kernel.org/r/20230511170202.742087-2-alexis.lothore%40bootlin.com
patch subject: [PATCH net v2 1/3] net: dsa: rzn1-a5psw: enable management frames for CPU port
config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20230512/202305121153.NMzdkguI-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/1a3acdd4d7ad50be9d4df989592327668610b13a
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review alexis-lothore-bootlin-com/net-dsa-rzn1-a5psw-enable-management-frames-for-CPU-port/20230512-010530
git checkout 1a3acdd4d7ad50be9d4df989592327668610b13a
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305121153.NMzdkguI-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/net/dsa/rzn1_a5psw.c: In function 'a5psw_setup':
>> drivers/net/dsa/rzn1_a5psw.c:676:32: error: 'A5PSW_MGMT_CFG_ENABLE' undeclared (first use in this function); did you mean 'A5PSW_MGMT_TAG_CFG_ENABLE'?
676 | reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_ENABLE;
| ^~~~~~~~~~~~~~~~~~~~~
| A5PSW_MGMT_TAG_CFG_ENABLE
drivers/net/dsa/rzn1_a5psw.c:676:32: note: each undeclared identifier is reported only once for each function it appears in
vim +676 drivers/net/dsa/rzn1_a5psw.c
659
660 static int a5psw_setup(struct dsa_switch *ds)
661 {
662 struct a5psw *a5psw = ds->priv;
663 int port, vlan, ret;
664 struct dsa_port *dp;
665 u32 reg;
666
667 /* Validate that there is only 1 CPU port with index A5PSW_CPU_PORT */
668 dsa_switch_for_each_cpu_port(dp, ds) {
669 if (dp->index != A5PSW_CPU_PORT) {
670 dev_err(a5psw->dev, "Invalid CPU port\n");
671 return -EINVAL;
672 }
673 }
674
675 /* Configure management port */
> 676 reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_ENABLE;
677 a5psw_reg_writel(a5psw, A5PSW_MGMT_CFG, reg);
678
679 /* Set pattern 0 to forward all frame to mgmt port */
680 a5psw_reg_writel(a5psw, A5PSW_PATTERN_CTRL(A5PSW_PATTERN_MGMTFWD),
681 A5PSW_PATTERN_CTRL_MGMTFWD);
682
683 /* Enable port tagging */
684 reg = FIELD_PREP(A5PSW_MGMT_TAG_CFG_TAGFIELD, ETH_P_DSA_A5PSW);
685 reg |= A5PSW_MGMT_TAG_CFG_ENABLE | A5PSW_MGMT_TAG_CFG_ALL_FRAMES;
686 a5psw_reg_writel(a5psw, A5PSW_MGMT_TAG_CFG, reg);
687
688 /* Enable normal switch operation */
689 reg = A5PSW_LK_ADDR_CTRL_BLOCKING | A5PSW_LK_ADDR_CTRL_LEARNING |
690 A5PSW_LK_ADDR_CTRL_AGEING | A5PSW_LK_ADDR_CTRL_ALLOW_MIGR |
691 A5PSW_LK_ADDR_CTRL_CLEAR_TABLE;
692 a5psw_reg_writel(a5psw, A5PSW_LK_CTRL, reg);
693
694 ret = readl_poll_timeout(a5psw->base + A5PSW_LK_CTRL, reg,
695 !(reg & A5PSW_LK_ADDR_CTRL_CLEAR_TABLE),
696 A5PSW_LK_BUSY_USEC_POLL, A5PSW_CTRL_TIMEOUT);
697 if (ret) {
698 dev_err(a5psw->dev, "Failed to clear lookup table\n");
699 return ret;
700 }
701
702 /* Reset learn count to 0 */
703 reg = A5PSW_LK_LEARNCOUNT_MODE_SET;
704 a5psw_reg_writel(a5psw, A5PSW_LK_LEARNCOUNT, reg);
705
706 /* Clear VLAN resource table */
707 reg = A5PSW_VLAN_RES_WR_PORTMASK | A5PSW_VLAN_RES_WR_TAGMASK;
708 for (vlan = 0; vlan < A5PSW_VLAN_COUNT; vlan++)
709 a5psw_reg_writel(a5psw, A5PSW_VLAN_RES(vlan), reg);
710
711 /* Reset all ports */
712 dsa_switch_for_each_port(dp, ds) {
713 port = dp->index;
714
715 /* Reset the port */
716 a5psw_reg_writel(a5psw, A5PSW_CMD_CFG(port),
717 A5PSW_CMD_CFG_SW_RESET);
718
719 /* Enable only CPU port */
720 a5psw_port_enable_set(a5psw, port, dsa_port_is_cpu(dp));
721
722 if (dsa_port_is_unused(dp))
723 continue;
724
725 /* Enable egress flooding for CPU port */
726 if (dsa_port_is_cpu(dp))
727 a5psw_flooding_set_resolution(a5psw, port, true);
728
729 /* Enable management forward only for user ports */
730 if (dsa_port_is_user(dp))
731 a5psw_port_mgmtfwd_set(a5psw, port, true);
732 }
733
734 return 0;
735 }
736
diff --git a/drivers/net/dsa/rzn1_a5psw.c b/drivers/net/dsa/rzn1_a5psw.c index 919027cf2012..8a419e2ffe2a 100644 --- a/drivers/net/dsa/rzn1_a5psw.c +++ b/drivers/net/dsa/rzn1_a5psw.c @@ -673,7 +673,7 @@ static int a5psw_setup(struct dsa_switch *ds) } /* Configure management port */ - reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_DISCARD; + reg = A5PSW_CPU_PORT | A5PSW_MGMT_CFG_ENABLE; a5psw_reg_writel(a5psw, A5PSW_MGMT_CFG, reg); /* Set pattern 0 to forward all frame to mgmt port */