Message ID | 20230726112458.3524165-1-haibo.chen@nxp.com (mailing list archive) |
---|---|
State | Awaiting Upstream |
Headers | show |
Series | [v3,1/2] arm64: dts: imx93: add the Flex-CAN stop mode by GPR | expand |
On 26.07.2023 19:24:57, haibo.chen@nxp.com wrote: > From: Haibo Chen <haibo.chen@nxp.com> > > imx93 A0 chip use the internal q-channel handshake signal in LPCG > and CCM to automatically handle the Flex-CAN stop mode. But this > method meet issue when do the system PM stress test. IC can't fix > it easily. So in the new imx93 A1 chip, IC drop this method, and > involve back the old way,use the GPR method to trigger the Flex-CAN > stop mode signal. Now NXP claim to drop imx93 A0, and only support > imx93 A1. So here add the stop mode through GPR. > > This patch also fix a typo for aonmix_ns_gpr. > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Added both to linux-can/testing. Thanks, Marc
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 4ec9df78f205..e0282c4ba11d 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -185,7 +185,7 @@ aips1: bus@44000000 { #size-cells = <1>; ranges; - anomix_ns_gpr: syscon@44210000 { + aonmix_ns_gpr: syscon@44210000 { compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; reg = <0x44210000 0x1000>; }; @@ -319,6 +319,7 @@ flexcan1: can@443a0000 { assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; status = "disabled"; }; @@ -591,6 +592,7 @@ flexcan2: can@425b0000 { assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; status = "disabled"; };