From patchwork Wed Aug 9 16:49:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13348209 X-Patchwork-Delegate: kuba@kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CDE91CA1D for ; Wed, 9 Aug 2023 17:01:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC994C43395; Wed, 9 Aug 2023 17:01:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1691600514; bh=xPpxwJzBLsCaca6qQZWRTcviG5VQc7YuCxtBnfOO0Sc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ftjeWrM2vszKk0pjhd+iTUqKRNmgdY1xZjDlMzt5r946dcWZeTuzXpMXhTWepbwms FEyiMj65e6ZxDlJsDTz6TLJHsZUq/TGnRIy8xcd0VxzDf92xW/rZSjSvAb3scYb/od rzqe5DdkB81Dg+uPVTqCgeOzEoGH1+1J2JDsKgsDhpVf6nLCCbHivao/q9iuIKc1wr EEk77jrxEbC7B5sn6dFiQAGCRNC8XnAhX8hpGw3o0qWlY+3nqumnfRojn4UISfTW9m fOx+ywo9pD1aFXWEc6YK/OnGP/5bslpHQyanjdby3W++CMvpCH3lJVTf8sGOQWpIsx nOcbFtlOD+6IA== From: Jisheng Zhang To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v3 02/10] net: stmmac: xgmac: add more feature parsing from hw cap Date: Thu, 10 Aug 2023 00:49:59 +0800 Message-Id: <20230809165007.1439-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230809165007.1439-1-jszhang@kernel.org> References: <20230809165007.1439-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The XGMAC_HWFEAT_GMIISEL bit also indicates whether support 10/100Mbps or not. The XGMAC_HWFEAT_HDSEL bit indicates whether support half duplex or not. The XGMAC_HWFEAT_ADDMACADRSEL bit indicates whether support Multiple MAC address registers or not. The XGMAC_HWFEAT_SMASEL bit indicates whether support SMA (MDIO) Interface or not. Signed-off-by: Jisheng Zhang Acked-by: Alexandre TORGUE --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 3 +++ drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 153321fe42c3..81cbb13a101d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -111,6 +111,7 @@ #define XGMAC_LPI_TIMER_CTRL 0x000000d4 #define XGMAC_HW_FEATURE0 0x0000011c #define XGMAC_HWFEAT_SAVLANINS BIT(27) +#define XGMAC_HWFEAT_ADDMACADRSEL GENMASK(22, 18) #define XGMAC_HWFEAT_RXCOESEL BIT(16) #define XGMAC_HWFEAT_TXCOESEL BIT(14) #define XGMAC_HWFEAT_EEESEL BIT(13) @@ -121,7 +122,9 @@ #define XGMAC_HWFEAT_MMCSEL BIT(8) #define XGMAC_HWFEAT_MGKSEL BIT(7) #define XGMAC_HWFEAT_RWKSEL BIT(6) +#define XGMAC_HWFEAT_SMASEL BIT(5) #define XGMAC_HWFEAT_VLHASH BIT(4) +#define XGMAC_HWFEAT_HDSEL BIT(3) #define XGMAC_HWFEAT_GMIISEL BIT(1) #define XGMAC_HW_FEATURE1 0x00000120 #define XGMAC_HWFEAT_L3L4FNUM GENMASK(30, 27) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index b09395f5edcb..b5ba4e0cca55 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -406,6 +406,10 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr, dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6; dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4; dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; + dma_cap->mbps_10_100 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; + dma_cap->half_duplex = (hw_cap & XGMAC_HWFEAT_HDSEL) >> 3; + dma_cap->multi_addr = (hw_cap & XGMAC_HWFEAT_ADDMACADRSEL) >> 18; + dma_cap->sma_mdio = (hw_cap & XGMAC_HWFEAT_SMASEL) >> 5; /* MAC HW feature 1 */ hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);