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[34.242.166.189]) by smtp.gmail.com with ESMTPSA id e15-20020a5d594f000000b00317df42e91dsm13921794wri.4.2023.09.12.15.46.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 15:47:00 -0700 (PDT) From: Puranjay Mohan To: Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Shubham Bansal , Russell King , "James E.J. Bottomley" , Helge Deller , "Naveen N. Rao" , Michael Ellerman , Nicholas Piggin , Christophe Leroy , Luke Nelson , Xi Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Wang YanQing , bpf@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org Cc: puranjay12@gmail.com Subject: [PATCH bpf-next 4/6] bpf, powerpc32: Always zero extend for LDX Date: Tue, 12 Sep 2023 22:46:52 +0000 Message-Id: <20230912224654.6556-5-puranjay12@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230912224654.6556-1-puranjay12@gmail.com> References: <20230912224654.6556-1-puranjay12@gmail.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: bpf@iogearbox.net The JITs should not depend on the verifier for zero extending the upper 32 bits of the destination register when loading a byte, half-word, or word. A following patch will make the verifier stop patching zext instructions after LDX. Signed-off-by: Puranjay Mohan --- arch/powerpc/net/bpf_jit_comp32.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c index 7f91ea064c08..0a952a2cfaac 100644 --- a/arch/powerpc/net/bpf_jit_comp32.c +++ b/arch/powerpc/net/bpf_jit_comp32.c @@ -936,14 +936,13 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * PPC_BCC_SHORT(COND_GT, (ctx->idx + 4) * 4); EMIT(PPC_RAW_LI(dst_reg, 0)); /* - * For BPF_DW case, "li reg_h,0" would be needed when - * !fp->aux->verifier_zext. Emit NOP otherwise. + * For BPF_DW case, "li reg_h,0" would be needed emit NOP otherwise. * * Note that "li reg_h,0" is emitted for BPF_B/H/W case, * if necessary. So, jump there insted of emitting an * additional "li reg_h,0" instruction. */ - if (size == BPF_DW && !fp->aux->verifier_zext) + if (size == BPF_DW) EMIT(PPC_RAW_LI(dst_reg_h, 0)); else EMIT(PPC_RAW_NOP()); @@ -974,7 +973,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * break; } - if (size != BPF_DW && !fp->aux->verifier_zext) + if (size != BPF_DW) EMIT(PPC_RAW_LI(dst_reg_h, 0)); if (BPF_MODE(code) == BPF_PROBE_MEM) { @@ -982,20 +981,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * int jmp_off = 4; /* - * In case of BPF_DW, two lwz instructions are emitted, one - * for higher 32-bit and another for lower 32-bit. So, set - * ex->insn to the first of the two and jump over both - * instructions in fixup. - * - * Similarly, with !verifier_zext, two instructions are - * emitted for BPF_B/H/W case. So, set ex->insn to the - * instruction that could fault and skip over both - * instructions. + * Two instructions are emitted for LDX. + * So, set ex->insn to the instruction that could fault and skip + * over both instructions. */ - if (size == BPF_DW || !fp->aux->verifier_zext) { - insn_idx -= 1; - jmp_off += 4; - } + insn_idx -= 1; + jmp_off += 4; ret = bpf_add_extable_entry(fp, image, pass, ctx, insn_idx, jmp_off, dst_reg);