From patchwork Fri Sep 29 14:12:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 13404308 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7A524E284 for ; Fri, 29 Sep 2023 14:13:19 +0000 (UTC) Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B1581BB for ; Fri, 29 Sep 2023 07:13:17 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4065f29e933so5697965e9.1 for ; Fri, 29 Sep 2023 07:13:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1695996796; x=1696601596; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tygpmxkKpMSdICit1qShK3ZZjtEq4RFKUNN+V0vvjrQ=; b=hfaBzMTA/pAf0CEdtGspu26m2HMwO9jSieasg7dDMK7z6jkdvCho0g9jpMI2eJIxWO ronQv1xOzyzN851GQOX74Mf3ZjpIapvyHUUeN6CgN50/zQv+bxDB+Wayd0AUa3GACH6q Z4+HbCLYTVcZWMr9nO5K+XVuX1PRER8cqX5DHdp7n+c5EDEhfQtrzof5suIM43dFioSV FdGiyQLjw+1GZW+ARJpqhkqFPuyd9gvHjJf+QPWhdAM7gjpMOKKuHIflDa4X764MiHjf 8FA/6CA8o1PJWM6bqUvf7kn9B4J9TaT/astRPrGWwDHLqFMs7uwwcgzu3bUa1Wfpn/8R ujkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695996796; x=1696601596; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tygpmxkKpMSdICit1qShK3ZZjtEq4RFKUNN+V0vvjrQ=; b=nR11yRUQSiGN1P6UkWNJSApYb9Z5k68sIsERWtrUiJCMSyEZJhBJl2KClfu4antk1X DHu4FrkgiyXYCzM+S4IIEh0/YsmIq7z54/Zgfe++jRJh2g0gdamuag8Q/NMx5Ts8ogWi OD9Wi8dOpZ6aT+a9nx2Tjqp3UZdQJSwDZ78Afgg/4fSZGeME5OMS1YeGC9AdqiOSpl6n 1rAAhC8SdlM5S3kO8WFEg8HT0pCyc7K8a28pD5RTr5GruMFrMnT6YFieQkNC47NBmm5C 28Z28OM5QzC7IedpUh0IKz0vd2QLaQePawLSPInJjj87yPofLVNVhx4Gzd3nBk1WhF5V ORiA== X-Gm-Message-State: AOJu0YxZ/rNuL8dlA2ERqaVBxqSae3dITakNHHeNCVG5ygYn0vCMsYzM CnHyLdljqdN668nd6MrzHQ77xg== X-Google-Smtp-Source: AGHT+IE0slc+UK6Ou6FpwHUsnr0SX9vylqCEpIS0H1NKjt+5oQUOiaSff3PSrRGsYCBZaRXX7gyu/Q== X-Received: by 2002:a7b:c5c7:0:b0:405:3ab9:eb07 with SMTP id n7-20020a7bc5c7000000b004053ab9eb07mr4192119wmk.20.1695996795962; Fri, 29 Sep 2023 07:13:15 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4091:a246:8222:dbda:9cd9:39cc:f174]) by smtp.gmail.com with ESMTPSA id t25-20020a7bc3d9000000b00405391f485fsm1513068wmj.41.2023.09.29.07.13.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Sep 2023 07:13:15 -0700 (PDT) From: Markus Schneider-Pargmann To: Marc Kleine-Budde , Chandrasekar Ramakrishnan , Wolfgang Grandegger Cc: Vincent MAILHOL , Simon Horman , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Panis , Judith Mendez , Markus Schneider-Pargmann Subject: [PATCH v6 05/14] can: m_can: Implement transmit coalescing Date: Fri, 29 Sep 2023 16:12:55 +0200 Message-Id: <20230929141304.3934380-6-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230929141304.3934380-1-msp@baylibre.com> References: <20230929141304.3934380-1-msp@baylibre.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Extend the coalescing implementation for transmits. In normal mode the chip raises an interrupt for every finished transmit. This implementation switches to coalescing mode as soon as an interrupt handled a transmit. For coalescing the watermark level interrupt is used to interrupt exactly after x frames were sent. It switches back into normal mode once there was an interrupt with no finished transmit and the timer being inactive. The timer is shared with receive coalescing. The time for receive and transmit coalescing timers have to be the same for that to work. The benefit is to have only a single running timer. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: Simon Horman --- drivers/net/can/m_can/m_can.c | 33 ++++++++++++++++++++------------- drivers/net/can/m_can/m_can.h | 4 ++++ 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 4492fe0da29c..b20edd64bb7e 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -255,6 +255,7 @@ enum m_can_reg { #define TXESC_TBDS_64B 0x7 /* Tx Event FIFO Configuration (TXEFC) */ +#define TXEFC_EFWM_MASK GENMASK(29, 24) #define TXEFC_EFS_MASK GENMASK(21, 16) /* Tx Event FIFO Status (TXEFS) */ @@ -432,7 +433,7 @@ static void m_can_interrupt_enable(struct m_can_classdev *cdev, u32 interrupts) static void m_can_coalescing_disable(struct m_can_classdev *cdev) { - u32 new_interrupts = cdev->active_interrupts | IR_RF0N; + u32 new_interrupts = cdev->active_interrupts | IR_RF0N | IR_TEFN; if (!cdev->net->irq) return; @@ -1114,24 +1115,29 @@ static int m_can_echo_tx_event(struct net_device *dev) static void m_can_coalescing_update(struct m_can_classdev *cdev, u32 ir) { u32 new_interrupts = cdev->active_interrupts; - bool enable_timer = false; + bool enable_rx_timer = false; + bool enable_tx_timer = false; if (!cdev->net->irq) return; if (cdev->rx_coalesce_usecs_irq > 0 && (ir & (IR_RF0N | IR_RF0W))) { - enable_timer = true; + enable_rx_timer = true; new_interrupts &= ~IR_RF0N; - } else if (!hrtimer_active(&cdev->hrtimer)) { - new_interrupts |= IR_RF0N; } + if (cdev->tx_coalesce_usecs_irq > 0 && (ir & (IR_TEFN | IR_TEFW))) { + enable_tx_timer = true; + new_interrupts &= ~IR_TEFN; + } + if (!enable_rx_timer && !hrtimer_active(&cdev->hrtimer)) + new_interrupts |= IR_RF0N; + if (!enable_tx_timer && !hrtimer_active(&cdev->hrtimer)) + new_interrupts |= IR_TEFN; m_can_interrupt_enable(cdev, new_interrupts); - if (enable_timer) { - hrtimer_start(&cdev->hrtimer, - ns_to_ktime(cdev->rx_coalesce_usecs_irq * NSEC_PER_USEC), + if (enable_rx_timer | enable_tx_timer) + hrtimer_start(&cdev->hrtimer, cdev->irq_timer_wait, HRTIMER_MODE_REL); - } } static irqreturn_t m_can_isr(int irq, void *dev_id) @@ -1186,7 +1192,7 @@ static irqreturn_t m_can_isr(int irq, void *dev_id) netif_wake_queue(dev); } } else { - if (ir & IR_TEFN) { + if (ir & (IR_TEFN | IR_TEFW)) { /* New TX FIFO Element arrived */ if (m_can_echo_tx_event(dev) != 0) goto out_fail; @@ -1354,9 +1360,8 @@ static int m_can_chip_config(struct net_device *dev) } /* Disable unused interrupts */ - interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TEFW | IR_TFE | - IR_TCF | IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N | - IR_RF0F); + interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TFE | IR_TCF | + IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N | IR_RF0F); m_can_config_endisable(cdev, true); @@ -1393,6 +1398,8 @@ static int m_can_chip_config(struct net_device *dev) } else { /* Full TX Event FIFO is used */ m_can_write(cdev, M_CAN_TXEFC, + FIELD_PREP(TXEFC_EFWM_MASK, + cdev->tx_max_coalesced_frames_irq) | FIELD_PREP(TXEFC_EFS_MASK, cdev->mcfg[MRAM_TXE].num) | cdev->mcfg[MRAM_TXE].off); diff --git a/drivers/net/can/m_can/m_can.h b/drivers/net/can/m_can/m_can.h index b916206199f1..1e461d305bce 100644 --- a/drivers/net/can/m_can/m_can.h +++ b/drivers/net/can/m_can/m_can.h @@ -84,6 +84,8 @@ struct m_can_classdev { struct sk_buff *tx_skb; struct phy *transceiver; + ktime_t irq_timer_wait; + struct m_can_ops *ops; int version; @@ -96,6 +98,8 @@ struct m_can_classdev { u32 active_interrupts; u32 rx_max_coalesced_frames_irq; u32 rx_coalesce_usecs_irq; + u32 tx_max_coalesced_frames_irq; + u32 tx_coalesce_usecs_irq; struct mram_cfg mcfg[MRAM_CFG_NUM];