@@ -19,7 +19,7 @@
struct octep_oq_desc_hw {
dma_addr_t buffer_ptr;
u64 info_ptr;
-};
+} __packed;
#define OCTEP_OQ_DESC_SIZE (sizeof(struct octep_oq_desc_hw))
@@ -38,7 +38,7 @@ struct octep_oq_resp_hw_ext {
/* checksum verified. */
u64 csum_verified:2;
-};
+} __packed;
#define OCTEP_OQ_RESP_HW_EXT_SIZE (sizeof(struct octep_oq_resp_hw_ext))
@@ -49,7 +49,7 @@ struct octep_oq_resp_hw_ext {
struct octep_oq_resp_hw {
/* The Length of the packet. */
__be64 length;
-};
+} __packed;
#define OCTEP_OQ_RESP_HW_SIZE (sizeof(struct octep_oq_resp_hw))
@@ -35,7 +35,7 @@
struct octep_tx_sglist_desc {
u16 len[4];
dma_addr_t dma_ptr[4];
-};
+} __packed;
/* Each Scatter/Gather entry sent to hardwar hold four pointers.
* So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1'
@@ -238,7 +238,7 @@ struct octep_instr_hdr {
/* Reserved3 */
u64 reserved3:1;
-};
+} __packed;
/* Hardware Tx completion response header */
struct octep_instr_resp_hdr {
@@ -262,7 +262,7 @@ struct octep_instr_resp_hdr {
/* Opcode for the return packet */
u64 opcode:16;
-};
+} __packed;
/* 64-byte Tx instruction format.
* Format of instruction for a 64-byte mode input queue.
@@ -292,7 +292,7 @@ struct octep_tx_desc_hw {
/* Additional headers available in a 64-byte instruction. */
u64 exhdr[4];
-};
+} __packed;
#define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw))
#endif /* _OCTEP_TX_H_ */
Add packed attribute to structures correlating to hardware data, as padding is not allowed by hardware. Signed-off-by: Shinas Rasheed <srasheed@marvell.com> --- V1 -> V2: Updated changelog drivers/net/ethernet/marvell/octeon_ep/octep_rx.h | 6 +++--- drivers/net/ethernet/marvell/octeon_ep/octep_tx.h | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-)