From patchwork Fri Oct 27 23:22:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Chan X-Patchwork-Id: 13439304 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51CDE405D8 for ; Fri, 27 Oct 2023 23:23:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="DZICHOfe" Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D925C2 for ; Fri, 27 Oct 2023 16:23:40 -0700 (PDT) Received: by mail-qk1-x72a.google.com with SMTP id af79cd13be357-778925998cbso190560185a.0 for ; Fri, 27 Oct 2023 16:23:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1698449019; x=1699053819; darn=vger.kernel.org; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=9WzFVVpQNPAFmfNlC5LZzZugsBo+VyZTi0s7fwSAytc=; b=DZICHOfedWw6yE158afvup9NTbbB4UYHbq2jcG+/8bcCtpzmX5sbOyLK/h2A2z0/yv Cqn1FuZGmTDcFUtelxU0axxFiTzprMCp/xm7edqvcW9CC6zltnDmJ9NObcso5bXu9PkF M+B5WbyRLVs3fC7QUoIxqVh2jl+Q3FVzUFIxE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698449019; x=1699053819; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9WzFVVpQNPAFmfNlC5LZzZugsBo+VyZTi0s7fwSAytc=; b=In0Aszytd5lmljxHvLFk4ibVVFwhH/dZKn1k8VX06GSlyRFTBRtvQdKkEPXU3X/3qy lwNQeVMl+b0yRk8/RpX7EcX5/Sgp0/jXGt16a9iDwKrldhQxLLQ0+iMddRolmrdoJy9C RNrcsVlaZUTsylmF3Egzd2lxAqx8rD3gl24an4sJqoT2XAZXHKpdC1r1S3Z+d48GYyUQ Sw20l5f9IYPhLii+Uvm3EoCqnPHk8JvSjbk+vENEjNysXWEd4DuglGMMwHkCuYDaP7Z2 LPq8hD6Y2CzLs8dv9TghBr2t1A/D9lNaq1iJsNFfKnQCS7XaE1mpZJXFvp2COngJ0PKW dHqw== X-Gm-Message-State: AOJu0YzisHLFsRoWbxcBwq5simdG2ey/AtlU9qa5/p5HKmoS822ihfTY ZFM6a4S6zSk412XBJZCIimkzFg== X-Google-Smtp-Source: AGHT+IHOR0ME6WetPegNrYvZibA9AAdL/fw3VH7REp6l5fcT05KqF8j8yooOa9VGRNUiM0agscgXCg== X-Received: by 2002:a05:620a:f85:b0:76e:f496:1930 with SMTP id b5-20020a05620a0f8500b0076ef4961930mr3515355qkn.43.1698449019466; Fri, 27 Oct 2023 16:23:39 -0700 (PDT) Received: from lvnvda5233.lvn.broadcom.net ([192.19.161.250]) by smtp.gmail.com with ESMTPSA id y27-20020a05620a09db00b007742ad3047asm984169qky.54.2023.10.27.16.23.38 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Oct 2023 16:23:39 -0700 (PDT) From: Michael Chan To: davem@davemloft.net Cc: netdev@vger.kernel.org, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, gospo@broadcom.com, Andy Gospodarek Subject: [PATCH net-next 05/13] bnxt_en: Remove BNXT_RX_HDL and BNXT_TX_HDL Date: Fri, 27 Oct 2023 16:22:44 -0700 Message-Id: <20231027232252.36111-6-michael.chan@broadcom.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20231027232252.36111-1-michael.chan@broadcom.com> References: <20231027232252.36111-1-michael.chan@broadcom.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org These 2 constants were used for the one RX and one TX completion ring pointer in the cpr->cp_ring_arr fixed array. Now that we've changed to allocating the array for the exact number of entries to support more TX rings, we no longer use these constants. The array index as well as the type of completion ring (RX/TX) are now encoded in the handle for the completion ring. This will allow us to locate the completion ring during NAPI for any number of completion rings sharing the same MSIX. In the following patches, we'll be adding support for more TX rings associated with the same MSIX vector. Reviewed-by: Andy Gospodarek Signed-off-by: Michael Chan --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 51 +++++++++++++---------- drivers/net/ethernet/broadcom/bnxt/bnxt.h | 17 +++++++- 2 files changed, 44 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index 11a85cb28517..a4f7fa17daf8 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -2906,12 +2906,15 @@ static int bnxt_poll_p5(struct napi_struct *napi, int budget) if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) { u32 idx = le32_to_cpu(nqcmp->cq_handle_low); + u32 cq_type = BNXT_NQ_HDL_TYPE(idx); struct bnxt_cp_ring_info *cpr2; /* No more budget for RX work */ - if (budget && work_done >= budget && idx == BNXT_RX_HDL) + if (budget && work_done >= budget && + cq_type == BNXT_NQ_HDL_TYPE_RX) break; + idx = BNXT_NQ_HDL_IDX(idx); cpr2 = &cpr->cp_ring_arr[idx]; work_done += __bnxt_poll_work(bp, cpr2, budget - work_done); @@ -2927,8 +2930,9 @@ static int bnxt_poll_p5(struct napi_struct *napi, int budget) BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons); } poll_done: - cpr_rx = &cpr->cp_ring_arr[BNXT_RX_HDL]; - if (cpr_rx->bnapi && (bp->flags & BNXT_FLAG_DIM)) { + cpr_rx = &cpr->cp_ring_arr[0]; + if (cpr_rx->cp_ring_type == BNXT_NQ_HDL_TYPE_RX && + (bp->flags & BNXT_FLAG_DIM)) { struct dim_sample dim_sample = {}; dim_update_sample(cpr->event_ctr, @@ -3592,6 +3596,7 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp) struct bnxt_napi *bnapi = bp->bnapi[i]; struct bnxt_cp_ring_info *cpr, *cpr2; struct bnxt_ring_struct *ring; + int cp_count = 0, k; if (!bnapi) continue; @@ -3612,30 +3617,32 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp) if (!(bp->flags & BNXT_FLAG_CHIP_P5)) continue; - cpr->cp_ring_count = 2; - cpr->cp_ring_arr = kcalloc(cpr->cp_ring_count, sizeof(*cpr), + if (i < bp->rx_nr_rings) + cp_count++; + if ((sh && i < bp->tx_nr_rings) || + (!sh && i >= bp->rx_nr_rings)) + cp_count++; + + cpr->cp_ring_arr = kcalloc(cp_count, sizeof(*cpr), GFP_KERNEL); - if (!cpr->cp_ring_arr) { - cpr->cp_ring_count = 0; + if (!cpr->cp_ring_arr) return -ENOMEM; - } + cpr->cp_ring_count = cp_count; - if (i < bp->rx_nr_rings) { - cpr2 = &cpr->cp_ring_arr[BNXT_RX_HDL]; - rc = bnxt_alloc_cp_sub_ring(bp, cpr2); - if (rc) - return rc; - cpr2->bnapi = bnapi; - bp->rx_ring[i].rx_cpr = cpr2; - } - if ((sh && i < bp->tx_nr_rings) || - (!sh && i >= bp->rx_nr_rings)) { - cpr2 = &cpr->cp_ring_arr[BNXT_TX_HDL]; + for (k = 0; k < cp_count; k++) { + cpr2 = &cpr->cp_ring_arr[k]; rc = bnxt_alloc_cp_sub_ring(bp, cpr2); if (rc) return rc; cpr2->bnapi = bnapi; - bp->tx_ring[j++].tx_cpr = cpr2; + cpr2->cp_idx = k; + if (!k && i < bp->rx_nr_rings) { + bp->rx_ring[i].rx_cpr = cpr2; + cpr2->cp_ring_type = BNXT_NQ_HDL_TYPE_RX; + } else { + bp->tx_ring[j++].tx_cpr = cpr2; + cpr2->cp_ring_type = BNXT_NQ_HDL_TYPE_TX; + } } } return 0; @@ -6023,7 +6030,7 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp) u32 type2 = HWRM_RING_ALLOC_CMPL; ring = &cpr2->cp_ring_struct; - ring->handle = BNXT_TX_HDL; + ring->handle = BNXT_SET_NQ_HDL(cpr2); map_idx = bnapi->index; rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); if (rc) @@ -6060,7 +6067,7 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp) u32 type2 = HWRM_RING_ALLOC_CMPL; ring = &cpr2->cp_ring_struct; - ring->handle = BNXT_RX_HDL; + ring->handle = BNXT_SET_NQ_HDL(cpr2); rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx); if (rc) goto err_out; diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h index c04089e7ac39..efb0db54575b 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h @@ -543,6 +543,19 @@ struct nqe_cn { __le32 cq_handle_high; }; +#define BNXT_NQ_HDL_IDX_MASK 0x00ffffff +#define BNXT_NQ_HDL_TYPE_MASK 0xff000000 +#define BNXT_NQ_HDL_TYPE_SHIFT 24 +#define BNXT_NQ_HDL_TYPE_RX 0x00 +#define BNXT_NQ_HDL_TYPE_TX 0x01 + +#define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK) +#define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \ + BNXT_NQ_HDL_TYPE_SHIFT) + +#define BNXT_SET_NQ_HDL(cpr) \ + (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx) + #define DB_IDX_MASK 0xffffff #define DB_IDX_VALID (0x1 << 26) #define DB_IRQ_DIS (0x1 << 27) @@ -997,6 +1010,8 @@ struct bnxt_cp_ring_info { u8 had_work_done:1; u8 has_more_work:1; + u8 cp_ring_type; + u8 cp_idx; u32 last_cp_raw_cons; @@ -1023,8 +1038,6 @@ struct bnxt_cp_ring_info { int cp_ring_count; struct bnxt_cp_ring_info *cp_ring_arr; -#define BNXT_RX_HDL 0 -#define BNXT_TX_HDL 1 }; struct bnxt_napi {