| Message ID | 20231103234658.511859-3-jacob.e.keller@intel.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | ice: restore timestamp config after reset | expand |
On Fri, Nov 03, 2023 at 04:46:57PM -0700, Jacob Keller wrote: > Commit d938a8cca88a ("ice: Auxbus devices & driver for E822 TS") modified > how Tx timestamps are handled for E822 devices. On these devices, only the > clock owner handles reading the Tx timestamp data from firmware. To do > this, the PFINT_TSYN_MSK register is modified from the default value to one > which enables reacting to a Tx timestamp on all PHY ports. > > The driver currently programs PFINT_TSYN_MSK in different places depending > on whether the port is the clock owner or not. For the clock owner, the > PFINT_TSYN_MSK value is programmed during ice_ptp_init_owner just before > calling ice_ptp_tx_ena_intr to program the PHY ports. > > For the non-clock owner ports, the PFINT_TSYN_MSK is programmed during > ice_ptp_init_port. > > If a large enough device reset occurs, the PFINT_TSYN_MSK register will be > reset to the default value in which only the PHY associated directly with > the PF will cause the Tx timestamp interrupt to trigger. > > The driver lacks logic to reprogram the PFINT_TSYN_MSK register after a > device reset. For the E822 device, this results in the PF no longer > responding to interrupts for other ports. This results in failure to > deliver Tx timestamps to user space applications. > > Rename ice_ptp_configure_tx_tstamp to ice_ptp_cfg_tx_interrupt, and unify > the logic for programming PFINT_TSYN_MSK and PFINT_OICR_ENA into one place. > This function will program both registers according to the combination of > user configuration and device requirements. > > This ensures that PFINT_TSYN_MSK is always restored when we configure the > Tx timestamp interrupt. > > Fixes: d938a8cca88a ("ice: Auxbus devices & driver for E822 TS") > Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> > Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Reviewed-by: Simon Horman <horms@kernel.org>
> -----Original Message----- > From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Jacob Keller > Sent: Saturday, November 4, 2023 5:17 AM > To: Nguyen, Anthony L <anthony.l.nguyen@intel.com> > Cc: Keller, Jacob E <jacob.e.keller@intel.com>; netdev@vger.kernel.org; Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Brandeburg, Jesse <jesse.brandeburg@intel.com> > Subject: [Intel-wired-lan] [PATCH iwl-net 2/3] ice: unify logic for programming PFINT_TSYN_MSK > > Commit d938a8cca88a ("ice: Auxbus devices & driver for E822 TS") modified > how Tx timestamps are handled for E822 devices. On these devices, only the > clock owner handles reading the Tx timestamp data from firmware. To do > this, the PFINT_TSYN_MSK register is modified from the default value to one > which enables reacting to a Tx timestamp on all PHY ports. > > The driver currently programs PFINT_TSYN_MSK in different places depending > on whether the port is the clock owner or not. For the clock owner, the > PFINT_TSYN_MSK value is programmed during ice_ptp_init_owner just before > calling ice_ptp_tx_ena_intr to program the PHY ports. > > For the non-clock owner ports, the PFINT_TSYN_MSK is programmed during > ice_ptp_init_port. > > If a large enough device reset occurs, the PFINT_TSYN_MSK register will be > reset to the default value in which only the PHY associated directly with > the PF will cause the Tx timestamp interrupt to trigger. > > The driver lacks logic to reprogram the PFINT_TSYN_MSK register after a > device reset. For the E822 device, this results in the PF no longer > responding to interrupts for other ports. This results in failure to > deliver Tx timestamps to user space applications. > > Rename ice_ptp_configure_tx_tstamp to ice_ptp_cfg_tx_interrupt, and unify > the logic for programming PFINT_TSYN_MSK and PFINT_OICR_ENA into one place. > This function will program both registers according to the combination of > user configuration and device requirements. > > This ensures that PFINT_TSYN_MSK is always restored when we configure the > Tx timestamp interrupt. > > Fixes: d938a8cca88a ("ice: Auxbus devices & driver for E822 TS") > Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> > Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com> > --- > drivers/net/ethernet/intel/ice/ice_ptp.c | 60 ++++++++++++++---------- > 1 file changed, 34 insertions(+), 26 deletions(-) > Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index affd90622a68..624d05b4bbd9 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -256,21 +256,42 @@ ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin, } /** - * ice_ptp_configure_tx_tstamp - Enable or disable Tx timestamp interrupt - * @pf: The PF pointer to search in - * @on: bool value for whether timestamp interrupt is enabled or disabled + * ice_ptp_cfg_tx_interrupt - Configure Tx timestamp interrupt for the device + * @pf: Board private structure + * + * Program the device to respond appropriately to the Tx timestamp interrupt + * cause. */ -static void ice_ptp_configure_tx_tstamp(struct ice_pf *pf, bool on) +static void ice_ptp_cfg_tx_interrupt(struct ice_pf *pf) { + struct ice_hw *hw = &pf->hw; + bool enable; u32 val; + switch (pf->ptp.tx_interrupt_mode) { + case ICE_PTP_TX_INTERRUPT_ALL: + /* React to interrupts across all quads. */ + wr32(hw, PFINT_TSYN_MSK + (0x4 * hw->pf_id), (u32)0x1f); + enable = true; + break; + case ICE_PTP_TX_INTERRUPT_NONE: + /* Do not react to interrupts on any quad. */ + wr32(hw, PFINT_TSYN_MSK + (0x4 * hw->pf_id), (u32)0x0); + enable = false; + break; + case ICE_PTP_TX_INTERRUPT_SELF: + default: + enable = pf->ptp.tstamp_config.tx_type == HWTSTAMP_TX_ON; + break; + } + /* Configure the Tx timestamp interrupt */ - val = rd32(&pf->hw, PFINT_OICR_ENA); - if (on) + val = rd32(hw, PFINT_OICR_ENA); + if (enable) val |= PFINT_OICR_TSYN_TX_M; else val &= ~PFINT_OICR_TSYN_TX_M; - wr32(&pf->hw, PFINT_OICR_ENA, val); + wr32(hw, PFINT_OICR_ENA, val); } /** @@ -280,10 +301,9 @@ static void ice_ptp_configure_tx_tstamp(struct ice_pf *pf, bool on) */ static void ice_set_tx_tstamp(struct ice_pf *pf, bool on) { - if (pf->ptp.tx_interrupt_mode == ICE_PTP_TX_INTERRUPT_SELF) - ice_ptp_configure_tx_tstamp(pf, on); - pf->ptp.tstamp_config.tx_type = on ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; + + ice_ptp_cfg_tx_interrupt(pf); } /** @@ -2789,15 +2809,7 @@ static int ice_ptp_init_owner(struct ice_pf *pf) /* Release the global hardware lock */ ice_ptp_unlock(hw); - if (pf->ptp.tx_interrupt_mode == ICE_PTP_TX_INTERRUPT_ALL) { - /* The clock owner for this device type handles the timestamp - * interrupt for all ports. - */ - ice_ptp_configure_tx_tstamp(pf, true); - - /* React on all quads interrupts for E82x */ - wr32(hw, PFINT_TSYN_MSK + (0x4 * hw->pf_id), (u32)0x1f); - + if (!ice_is_e810(hw)) { /* Enable quad interrupts */ err = ice_ptp_tx_ena_intr(pf, true, itr); if (err) @@ -2867,13 +2879,6 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port) case ICE_PHY_E810: return ice_ptp_init_tx_e810(pf, &ptp_port->tx); case ICE_PHY_E822: - /* Non-owner PFs don't react to any interrupts on E82x, - * neither on own quad nor on others - */ - if (!ice_ptp_pf_handles_tx_interrupt(pf)) { - ice_ptp_configure_tx_tstamp(pf, false); - wr32(hw, PFINT_TSYN_MSK + (0x4 * hw->pf_id), (u32)0x0); - } kthread_init_delayed_work(&ptp_port->ov_work, ice_ptp_wait_for_offsets); @@ -3018,6 +3023,9 @@ void ice_ptp_init(struct ice_pf *pf) /* Start the PHY timestamping block */ ice_ptp_reset_phy_timestamping(pf); + /* Configure initial Tx interrupt settings */ + ice_ptp_cfg_tx_interrupt(pf); + set_bit(ICE_FLAG_PTP, pf->flags); err = ice_ptp_init_work(pf, ptp); if (err)
Commit d938a8cca88a ("ice: Auxbus devices & driver for E822 TS") modified how Tx timestamps are handled for E822 devices. On these devices, only the clock owner handles reading the Tx timestamp data from firmware. To do this, the PFINT_TSYN_MSK register is modified from the default value to one which enables reacting to a Tx timestamp on all PHY ports. The driver currently programs PFINT_TSYN_MSK in different places depending on whether the port is the clock owner or not. For the clock owner, the PFINT_TSYN_MSK value is programmed during ice_ptp_init_owner just before calling ice_ptp_tx_ena_intr to program the PHY ports. For the non-clock owner ports, the PFINT_TSYN_MSK is programmed during ice_ptp_init_port. If a large enough device reset occurs, the PFINT_TSYN_MSK register will be reset to the default value in which only the PHY associated directly with the PF will cause the Tx timestamp interrupt to trigger. The driver lacks logic to reprogram the PFINT_TSYN_MSK register after a device reset. For the E822 device, this results in the PF no longer responding to interrupts for other ports. This results in failure to deliver Tx timestamps to user space applications. Rename ice_ptp_configure_tx_tstamp to ice_ptp_cfg_tx_interrupt, and unify the logic for programming PFINT_TSYN_MSK and PFINT_OICR_ENA into one place. This function will program both registers according to the combination of user configuration and device requirements. This ensures that PFINT_TSYN_MSK is always restored when we configure the Tx timestamp interrupt. Fixes: d938a8cca88a ("ice: Auxbus devices & driver for E822 TS") Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp.c | 60 ++++++++++++++---------- 1 file changed, 34 insertions(+), 26 deletions(-)