| Message ID | 20231201-feature_poe-v2-7-56d8cac607fa@bootlin.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: Add support for Power over Ethernet (PoE) | expand |
On Fri, Dec 01, 2023 at 06:10:29PM +0100, Kory Maincent wrote: > Add the PD692x0 I2C Power Sourcing Equipment controller device tree > bindings documentation. > > Sponsored-by: Dent Project <dentproject@linuxfoundation.org> > Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> > --- > > Changes in v2: > - Enhance ports-matrix description. > - Replace additionalProperties by unevaluatedProperties. > - Drop i2c suffix. > --- > .../bindings/net/pse-pd/microchip,pd692x0.yaml | 77 ++++++++++++++++++++++ > MAINTAINERS | 6 ++ > 2 files changed, 83 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml > new file mode 100644 > index 000000000000..3ce81cf99215 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PD692x0 Power Sourcing Equipment controller > + > +maintainers: > + - Kory Maincent <kory.maincent@bootlin.com> > + > +allOf: > + - $ref: pse-controller.yaml# > + > +properties: > + compatible: > + enum: > + - microchip,pd69200 > + - microchip,pd69210 > + - microchip,pd69220 > + > + reg: > + maxItems: 1 > + > + '#pse-cells': > + const: 1 > + > + ports-matrix: > + description: each set of 48 logical ports can be assigned to one or two > + physical ports. Each physical port is wired to a PD69204/8 PoE > + manager. Using two different PoE managers for one RJ45 port > + (logical port) is interesting for temperature dissipation. > + This parameter describes the configuration of the port conversion > + matrix that establishes the relationship between the 48 logical ports > + and the available 96 physical ports. Unspecified logical ports will > + be deactivated. > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + minItems: 1 > + maxItems: 48 > + items: > + items: > + - description: Logical port number > + minimum: 0 > + maximum: 47 > + - description: Physical port number A (0xff for undefined) > + oneOf: > + - minimum: 0 > + maximum: 95 > + - const: 0xff > + - description: Physical port number B (0xff for undefined) > + oneOf: > + - minimum: 0 > + maximum: 95 > + - const: 0xff > + > +unevaluatedProperties: false > + > +required: > + - compatible > + - reg > + > +examples: > + - | > + i2c { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethernet-pse@3c { > + compatible = "microchip,pd69200"; > + reg = <0x3c>; > + #pse-cells = <1>; > + ports-matrix = <0 2 5 > + 1 3 6 > + 2 0 0xff > + 3 1 0xff>; Hm... this will probably not scale. PSE is kind of PMIC for ethernet. I has bunch of regulators which can be grouped to one more powerful regulator. Since it is regulators, we will wont to represent them in a system as regulators too. We will probably have physical, board specific limitation, so we will need to describe regulator limits for each separate channel. > + }; > + }; > diff --git a/MAINTAINERS b/MAINTAINERS > index e3fd148d462e..b746684f3fd3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -14235,6 +14235,12 @@ L: linux-serial@vger.kernel.org > S: Maintained > F: drivers/tty/serial/8250/8250_pci1xxxx.c > > +MICROCHIP PD692X0 PSE DRIVER > +M: Kory Maincent <kory.maincent@bootlin.com> > +L: netdev@vger.kernel.org > +S: Maintained > +F: Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml > + > MICROCHIP POLARFIRE FPGA DRIVERS > M: Conor Dooley <conor.dooley@microchip.com> > R: Vladimir Georgiev <v.georgiev@metrotek.ru> > > -- > 2.25.1 > > >
CC regulator devs here. PSE is a regulator for network devices :) On Tue, Dec 05, 2023 at 12:08:45AM +0100, Oleksij Rempel wrote: > On Fri, Dec 01, 2023 at 06:10:29PM +0100, Kory Maincent wrote: > > Add the PD692x0 I2C Power Sourcing Equipment controller device tree > > bindings documentation. > > > > Sponsored-by: Dent Project <dentproject@linuxfoundation.org> > > Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> > > --- > > > > Changes in v2: > > - Enhance ports-matrix description. > > - Replace additionalProperties by unevaluatedProperties. > > - Drop i2c suffix. > > --- > > .../bindings/net/pse-pd/microchip,pd692x0.yaml | 77 ++++++++++++++++++++++ > > MAINTAINERS | 6 ++ > > 2 files changed, 83 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml > > new file mode 100644 > > index 000000000000..3ce81cf99215 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Microchip PD692x0 Power Sourcing Equipment controller > > + > > +maintainers: > > + - Kory Maincent <kory.maincent@bootlin.com> > > + > > +allOf: > > + - $ref: pse-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - microchip,pd69200 > > + - microchip,pd69210 > > + - microchip,pd69220 > > + > > + reg: > > + maxItems: 1 > > + > > + '#pse-cells': > > + const: 1 > > + > > + ports-matrix: > > + description: each set of 48 logical ports can be assigned to one or two > > + physical ports. Each physical port is wired to a PD69204/8 PoE > > + manager. Using two different PoE managers for one RJ45 port > > + (logical port) is interesting for temperature dissipation. > > + This parameter describes the configuration of the port conversion > > + matrix that establishes the relationship between the 48 logical ports > > + and the available 96 physical ports. Unspecified logical ports will > > + be deactivated. > > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > > + minItems: 1 > > + maxItems: 48 > > + items: > > + items: > > + - description: Logical port number > > + minimum: 0 > > + maximum: 47 > > + - description: Physical port number A (0xff for undefined) > > + oneOf: > > + - minimum: 0 > > + maximum: 95 > > + - const: 0xff > > + - description: Physical port number B (0xff for undefined) > > + oneOf: > > + - minimum: 0 > > + maximum: 95 > > + - const: 0xff > > + > > +unevaluatedProperties: false > > + > > +required: > > + - compatible > > + - reg > > + > > +examples: > > + - | > > + i2c { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + ethernet-pse@3c { > > + compatible = "microchip,pd69200"; > > + reg = <0x3c>; > > + #pse-cells = <1>; > > + ports-matrix = <0 2 5 > > + 1 3 6 > > + 2 0 0xff > > + 3 1 0xff>; > > Hm... this will probably not scale. PSE is kind of PMIC for ethernet. I > has bunch of regulators which can be grouped to one more powerful > regulator. Since it is regulators, we will wont to represent them in a > system as regulators too. We will probably have physical, board > specific limitation, so we will need to describe regulator limits for > each separate channel. After diving a bit deeper to the chip manual and communication protocol manual I would recommend to recreate system topology as good as possible in the devicetree. The reason is that we actually able to communicate with with "manager" behind the "controller" and the "port-matrix" is all about the "managers" and physical ports layout. Typical system architecture looks like this: SoC --- i2c/uart --> controller -- spi --> manager0 -- phys_port0 --> log_port0 (PoE4) | \- phys_port1 -/ | \- phys_port2 --> log_port1 (PoE2) | \- phys_port3 --> log_port2 (PoE2) \- manager1 -- phys_port0 .. .... Please include some ASCII topology to the documentation :) I would expect a devicetree like this: ethernet-pse@3c { // controller compatible should be precise compatible = "microchip,pd69210"; reg = <0x3c>; #pse-cells = <1>; managers { manager@0 { // manager compatible should be included, since we are // able to campare it with communication results compatible = "microchip,pd69208t4" // addressing corresponding to the chip select addressing reg = <0>; physical-ports { phys0: port@0 { // each of physical ports is actually a regulator reg = <0>; }; phys1: port@1 { reg = <1>; }; phys2: port@2 { reg = <2>; }; ... } // port matrix can be calculated by using this information logical-ports { log_port0: port@0 { // PoE4 port physical-ports = <&phys0, &phys1>; }; log_port1: port@1 { // PoE2 port physical-ports = <&phys2>; }; }; .... ethernet-phy@1 { reg = <1>; pses = <&log_port0>; } ethernet-phy@2 { reg = <2>; pses = <&log_port1>; }
On Tue, 5 Dec 2023 07:36:06 +0100 Oleksij Rempel <o.rempel@pengutronix.de> wrote: > > > +examples: > > > + - | > > > + i2c { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + ethernet-pse@3c { > > > + compatible = "microchip,pd69200"; > > > + reg = <0x3c>; > > > + #pse-cells = <1>; > > > + ports-matrix = <0 2 5 > > > + 1 3 6 > > > + 2 0 0xff > > > + 3 1 0xff>; > > > > Hm... this will probably not scale. PSE is kind of PMIC for ethernet. I > > has bunch of regulators which can be grouped to one more powerful > > regulator. Since it is regulators, we will wont to represent them in a > > system as regulators too. We will probably have physical, board > > specific limitation, so we will need to describe regulator limits for > > each separate channel. > > After diving a bit deeper to the chip manual and communication protocol > manual I would recommend to recreate system topology as good as possible > in the devicetree. The reason is that we actually able to communicate > with with "manager" behind the "controller" and the "port-matrix" is all > about the "managers" and physical ports layout. Ok, but the "managers communication" implementation will be added later as for now only the basics of the the PSE controller is implemented. > Typical system architecture looks like this: > > SoC --- i2c/uart --> controller -- spi --> manager0 -- phys_port0 --> > log_port0 (PoE4) | \- phys_port1 -/ > | \- phys_port2 --> > log_port1 (PoE2) | \- phys_port3 --> log_port2 (PoE2) > \- manager1 -- phys_port0 .. > .... > > Please include some ASCII topology to the documentation :) Ok. > I would expect a devicetree like this: > > ethernet-pse@3c { > // controller compatible should be precise > compatible = "microchip,pd69210"; > reg = <0x3c>; > #pse-cells = <1>; > > managers { > manager@0 { > // manager compatible should be included, since we are > // able to campare it with communication results > compatible = "microchip,pd69208t4" > // addressing corresponding to the chip select addressing > reg = <0>; > > physical-ports { > phys0: port@0 { > // each of physical ports is actually a regulator > reg = <0>; > }; > phys1: port@1 { > reg = <1>; > }; > phys2: port@2 { > reg = <2>; > }; > > ... > } > > // port matrix can be calculated by using this information > logical-ports { > log_port0: port@0 { > // PoE4 port > physical-ports = <&phys0, &phys1>; > }; > log_port1: port@1 { > // PoE2 port > physical-ports = <&phys2>; > }; > }; > > .... > ethernet-phy@1 { > reg = <1>; > pses = <&log_port0>; > } > ethernet-phy@2 { > reg = <2>; > pses = <&log_port1>; > } The pse node will become massive (more than 140 subnodes) but indeed this will fit the real topology architecture. Regards,
On Tue, Dec 05, 2023 at 07:36:06AM +0100, Oleksij Rempel wrote:
> CC regulator devs here. PSE is a regulator for network devices :)
Is there some question related to regulators here? I couldn't spot one.
On Tue, 5 Dec 2023 11:15:01 +0100 Köry Maincent <kory.maincent@bootlin.com> wrote: > On Tue, 5 Dec 2023 07:36:06 +0100 > Oleksij Rempel <o.rempel@pengutronix.de> wrote: > > I would expect a devicetree like this: > > > > ethernet-pse@3c { > > // controller compatible should be precise > > compatible = "microchip,pd69210"; > > reg = <0x3c>; > > #pse-cells = <1>; > > > > managers { > > manager@0 { > > // manager compatible should be included, since we are > > // able to campare it with communication results > > compatible = "microchip,pd69208t4" > > // addressing corresponding to the chip select addressing > > reg = <0>; > > > > physical-ports { > > phys0: port@0 { > > // each of physical ports is actually a regulator If this phys0 is a regulator, which device will be the consumer of this regulator? log_port0 as the phys0 regulator consumer seems a bit odd! A 8P8C node should be the consumer. > > reg = <0>; > > }; > > phys1: port@1 { > > reg = <1>; > > }; > > phys2: port@2 { > > reg = <2>; > > }; > > > > ... > > } > > > > // port matrix can be calculated by using this information > > logical-ports { > > log_port0: port@0 { > > // PoE4 port > > physical-ports = <&phys0, &phys1>; > > }; > > log_port1: port@1 { > > // PoE2 port > > physical-ports = <&phys2>; > > }; > > }; > > > > .... > > ethernet-phy@1 { > > reg = <1>; > > pses = <&log_port0>; > > } > > ethernet-phy@2 { > > reg = <2>; > > pses = <&log_port1>; > > } In fact if we want to really fit the PoE architecture topology we should wait for the support of 8P8C connector from Maxime. Then it will look like that: SoC --- i2c/uart --> controller -- spi --> manager0 -- phys_port0 --> 8P8C_connector0 (PoE4) | \- phys_port1 --> 8P8C_connector0 (PoE4) | \- phys_port2 --> 8P8C_connector1 (PoE2) | \- phys_port3 --> 8P8C_connector2 (PoE2) \- manager1 -- phys_port0 .. With this type of devicetree: ethernet-pse@3c { // controller compatible should be precise compatible = "microchip,pd69210"; reg = <0x3c>; #pse-cells = <1>; managers { manager@0 { // manager compatible should be included, since we are // able to compare it with communication results compatible = "microchip,pd69208t4" // addressing corresponding to the chip select addressing reg = <0>; physical-ports { phys_port0: port@0 { // each of physical ports is actually a regulator reg = <0>; }; phy_port1: port@1 { reg = <1>; }; phy_port2: port@2 { reg = <2>; }; ... } manager@1 { ... }; }; }; .... rj45_0:8p8c@0 { pses = <&phy_port0, &phy_port1>; }; rj45_1:8p8c@1 { pses = <&phy_port2>; }; ethernet-phy@1 { reg = <1>; connector = <&rj45_0>; }; ethernet-phy@2 { reg = <2>; connector = <&rj45_1>; } The drawback is that I don't really know for now, how port matrix can be calculated with this. Maybe by adding a "conf_pse_cell()" callback, call in the of_pse_control_get() for each ports. For now 8p8c connector are not supported, we could keep using pse phandle in the phy node like you described but for physical port: ethernet-phy@1 { reg = <1>; pses = <&phy_port0, &phy_port1>; } ethernet-phy@2 { reg = <2>; pses = <&phy_port2>; } Finally, the devicetree would not know the matrix between logical port and physical port, this would be cleaner. Did I miss something? Regards,
On Tue, Dec 05, 2023 at 02:31:23PM +0100, Köry Maincent wrote: > On Tue, 5 Dec 2023 11:15:01 +0100 > Köry Maincent <kory.maincent@bootlin.com> wrote: > > > On Tue, 5 Dec 2023 07:36:06 +0100 > > Oleksij Rempel <o.rempel@pengutronix.de> wrote: > > > > I would expect a devicetree like this: > > > > > > ethernet-pse@3c { > > > // controller compatible should be precise > > > compatible = "microchip,pd69210"; > > > reg = <0x3c>; > > > #pse-cells = <1>; > > > > > > managers { > > > manager@0 { > > > // manager compatible should be included, since we are > > > // able to campare it with communication results > > > compatible = "microchip,pd69208t4" > > > // addressing corresponding to the chip select addressing > > > reg = <0>; > > > > > > physical-ports { > > > phys0: port@0 { > > > // each of physical ports is actually a regulator > > If this phys0 is a regulator, which device will be the consumer of this > regulator? log_port0 as the phys0 regulator consumer seems a bit odd! Why? > A 8P8C node should be the consumer. PHY is not actual consumer of this regulator. State of the Ethernet PHY is not related to the power supply. We should deliver power independent of network interface state. There is no other local consumer we can use in this case. > > > reg = <0>; > > > }; > > > phys1: port@1 { > > > reg = <1>; > > > }; > > > phys2: port@2 { > > > reg = <2>; > > > }; > > > > > > ... > > > } > > > > > > // port matrix can be calculated by using this information > > > logical-ports { > > > log_port0: port@0 { > > > // PoE4 port > > > physical-ports = <&phys0, &phys1>; > > > }; > > > log_port1: port@1 { > > > // PoE2 port > > > physical-ports = <&phys2>; > > > }; > > > }; > > > > > > .... > > > ethernet-phy@1 { > > > reg = <1>; > > > pses = <&log_port0>; > > > } > > > ethernet-phy@2 { > > > reg = <2>; > > > pses = <&log_port1>; > > > } > > In fact if we want to really fit the PoE architecture topology we should wait > for the support of 8P8C connector from Maxime. Then it will look like that: > SoC --- i2c/uart --> controller -- spi --> manager0 -- phys_port0 --> 8P8C_connector0 (PoE4) > | \- phys_port1 --> 8P8C_connector0 (PoE4) > | \- phys_port2 --> 8P8C_connector1 (PoE2) > | \- phys_port3 --> 8P8C_connector2 (PoE2) > \- manager1 -- phys_port0 .. > > With this type of devicetree: > ethernet-pse@3c { > // controller compatible should be precise > compatible = "microchip,pd69210"; > reg = <0x3c>; > #pse-cells = <1>; > > managers { > manager@0 { > // manager compatible should be included, since we are > // able to compare it with communication results > compatible = "microchip,pd69208t4" > // addressing corresponding to the chip select addressing > reg = <0>; > > physical-ports { > phys_port0: port@0 { > // each of physical ports is actually a regulator > reg = <0>; > }; > phy_port1: port@1 { > reg = <1>; > }; > phy_port2: port@2 { > reg = <2>; > }; > > ... > } > manager@1 { > ... > }; > }; > }; > > .... > rj45_0:8p8c@0 { > pses = <&phy_port0, &phy_port1>; > }; > rj45_1:8p8c@1 { > pses = <&phy_port2>; > }; > ethernet-phy@1 { > reg = <1>; > connector = <&rj45_0>; > }; > ethernet-phy@2 { > reg = <2>; > connector = <&rj45_1>; > } > > > The drawback is that I don't really know for now, how port matrix can be > calculated with this. Maybe by adding a "conf_pse_cell()" callback, call > in the of_pse_control_get() for each ports. > > For now 8p8c connector are not supported, we could keep using pse phandle > in the phy node like you described but for physical port: > ethernet-phy@1 { > reg = <1>; > pses = <&phy_port0, &phy_port1>; > } > ethernet-phy@2 { > reg = <2>; > pses = <&phy_port2>; > } > > > > Finally, the devicetree would not know the matrix between logical port and > physical port, this would be cleaner. > > Did I miss something? In case different PSE suppliers are linked withing the PHY node, we loose most of information needed for PSE functionality. For example how we will know if our log_port supports PoE4 and PoE2 mode, or only PoE2. This information is vital for proper PSE configuration, this is why I suggested to have logica-ports subnodes. With the price of hawing huge DT on a switch with 48 ports.
On Tue, 5 Dec 2023 15:21:47 +0100 Oleksij Rempel <o.rempel@pengutronix.de> wrote: > On Tue, Dec 05, 2023 at 02:31:23PM +0100, Köry Maincent wrote: > > On Tue, 5 Dec 2023 11:15:01 +0100 > > Köry Maincent <kory.maincent@bootlin.com> wrote: > > > > > On Tue, 5 Dec 2023 07:36:06 +0100 > > > Oleksij Rempel <o.rempel@pengutronix.de> wrote: > > > > > > I would expect a devicetree like this: > > > > > > > > ethernet-pse@3c { > > > > // controller compatible should be precise > > > > compatible = "microchip,pd69210"; > > > > reg = <0x3c>; > > > > #pse-cells = <1>; > > > > > > > > managers { > > > > manager@0 { > > > > // manager compatible should be included, since we are > > > > // able to campare it with communication results > > > > compatible = "microchip,pd69208t4" > > > > // addressing corresponding to the chip select addressing > > > > reg = <0>; > > > > > > > > physical-ports { > > > > phys0: port@0 { > > > > // each of physical ports is actually a regulator > > > > If this phys0 is a regulator, which device will be the consumer of this > > regulator? log_port0 as the phys0 regulator consumer seems a bit odd! > > Why? > > > A 8P8C node should be the consumer. > > PHY is not actual consumer of this regulator. State of the Ethernet PHY > is not related to the power supply. We should deliver power independent > of network interface state. There is no other local consumer we can > use in this case. Just to be clear, are you saying we should use the regulator framework or is it simply a way of speaking as it behaves like regulator? > > Finally, the devicetree would not know the matrix between logical port and > > physical port, this would be cleaner. > > > > Did I miss something? > > In case different PSE suppliers are linked withing the PHY node, we > loose most of information needed for PSE functionality. For example how > we will know if our log_port supports PoE4 and PoE2 mode, or only PoE2. > This information is vital for proper PSE configuration, this is why I > suggested to have logica-ports subnodes. With the price of hawing huge > DT on a switch with 48 ports. It could be known in the of_pse_control_get() function if there is two phandles in the "pses" parameter. Then we add a new enum c33_pse_mode member in the pse_control struct to store the mode. PoE2 and PoE4 is not a parameter of the logical port, it depends of the number of PSE ports wired to an 8P8C connector. In fact I am also working on the tps23881 driver which aimed to be added to this series soon. In the tps23881 case the logical port can only be configured to one physical port. Two physical ports (which mean two logical ports) can still be used to have PoE4 mode. For PoE4, in the pd692x0 driver we use one logical port (one pse_control->id) configured to two physical ports but in the tps23881 we will need two logical ports (two pse_control->id). So with the tps23881 driver we will need two phandle in the "pses" parameter to have PoE4, that's why my proposition seems relevant. The same goes with your pse-regulator driver, you can't do PoE4 if two regulators is needed for each two pairs group. Regards,
On Tue, 5 Dec 2023 16:23:21 +0100 Köry Maincent <kory.maincent@bootlin.com> wrote: > On Tue, 5 Dec 2023 15:21:47 +0100 > Oleksij Rempel <o.rempel@pengutronix.de> wrote: > > > On Tue, Dec 05, 2023 at 02:31:23PM +0100, Köry Maincent wrote: > > > On Tue, 5 Dec 2023 11:15:01 +0100 > > > Köry Maincent <kory.maincent@bootlin.com> wrote: > > > > > > > On Tue, 5 Dec 2023 07:36:06 +0100 > > > > Oleksij Rempel <o.rempel@pengutronix.de> wrote: > > > > > > > > I would expect a devicetree like this: > > > > > > > > > > ethernet-pse@3c { > > > > > // controller compatible should be precise > > > > > compatible = "microchip,pd69210"; > > > > > reg = <0x3c>; > > > > > #pse-cells = <1>; > > > > > > > > > > managers { > > > > > manager@0 { > > > > > // manager compatible should be included, since we are > > > > > // able to campare it with communication results > > > > > compatible = "microchip,pd69208t4" > > > > > // addressing corresponding to the chip select > > > > > addressing reg = <0>; > > > > > > > > > > physical-ports { > > > > > phys0: port@0 { > > > > > // each of physical ports is actually a regulator > > > > > > > > > > > If this phys0 is a regulator, which device will be the consumer of this > > > regulator? log_port0 as the phys0 regulator consumer seems a bit odd! > > > > Why? > > > > > A 8P8C node should be the consumer. > > > > PHY is not actual consumer of this regulator. State of the Ethernet PHY > > is not related to the power supply. We should deliver power independent > > of network interface state. There is no other local consumer we can > > use in this case. > > Just to be clear, are you saying we should use the regulator framework or is > it simply a way of speaking as it behaves like regulator? > > > > Finally, the devicetree would not know the matrix between logical port and > > > physical port, this would be cleaner. > > > > > > Did I miss something? > > > > In case different PSE suppliers are linked withing the PHY node, we > > loose most of information needed for PSE functionality. For example how > > we will know if our log_port supports PoE4 and PoE2 mode, or only PoE2. > > This information is vital for proper PSE configuration, this is why I > > suggested to have logica-ports subnodes. With the price of hawing huge > > DT on a switch with 48 ports. > > It could be known in the of_pse_control_get() function if there is two > phandles in the "pses" parameter. Then we add a new enum c33_pse_mode member > in the pse_control struct to store the mode. > PoE2 and PoE4 is not a parameter of the logical port, it depends of the number > of PSE ports wired to an 8P8C connector. > > In fact I am also working on the tps23881 driver which aimed to be added to > this series soon. In the tps23881 case the logical port can only be configured > to one physical port. Two physical ports (which mean two logical ports) can > still be used to have PoE4 mode. > For PoE4, in the pd692x0 driver we use one logical port (one pse_control->id) > configured to two physical ports but in the tps23881 we will need two logical > ports (two pse_control->id). > > So with the tps23881 driver we will need two phandle in the "pses" parameter > to have PoE4, that's why my proposition seems relevant. > > The same goes with your pse-regulator driver, you can't do PoE4 if two > regulators is needed for each two pairs group. Oleksij, what your thought for the binding I have proposed in the thread. For the PoE4 we could add a "pses-poe4" bool property alongside the two phandle in "pses" property. Here is the current binding proposition: ethernet-pse@3c { // controller compatible should be precise compatible = "microchip,pd69210"; reg = <0x3c>; #pse-cells = <1>; managers { manager@0 { // manager compatible should be included, since we are // able to compare it with communication results compatible = "microchip,pd69208t4" // addressing corresponding to the chip select addressing reg = <0>; physical-ports { phys_port0: port@0 { // each of physical ports is actually a regulator reg = <0>; }; phy_port1: port@1 { reg = <1>; }; phy_port2: port@2 { reg = <2>; }; ... } manager@1 { ... }; }; }; .... ethernet-phy@1 { reg = <1>; pses-poe4; pses = <&phy_port0, &phy_port1>; }; ethernet-phy@2 { reg = <2>; pses = <&phy_port2>; } Regards,
diff --git a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml new file mode 100644 index 000000000000..3ce81cf99215 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PD692x0 Power Sourcing Equipment controller + +maintainers: + - Kory Maincent <kory.maincent@bootlin.com> + +allOf: + - $ref: pse-controller.yaml# + +properties: + compatible: + enum: + - microchip,pd69200 + - microchip,pd69210 + - microchip,pd69220 + + reg: + maxItems: 1 + + '#pse-cells': + const: 1 + + ports-matrix: + description: each set of 48 logical ports can be assigned to one or two + physical ports. Each physical port is wired to a PD69204/8 PoE + manager. Using two different PoE managers for one RJ45 port + (logical port) is interesting for temperature dissipation. + This parameter describes the configuration of the port conversion + matrix that establishes the relationship between the 48 logical ports + and the available 96 physical ports. Unspecified logical ports will + be deactivated. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 48 + items: + items: + - description: Logical port number + minimum: 0 + maximum: 47 + - description: Physical port number A (0xff for undefined) + oneOf: + - minimum: 0 + maximum: 95 + - const: 0xff + - description: Physical port number B (0xff for undefined) + oneOf: + - minimum: 0 + maximum: 95 + - const: 0xff + +unevaluatedProperties: false + +required: + - compatible + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-pse@3c { + compatible = "microchip,pd69200"; + reg = <0x3c>; + #pse-cells = <1>; + ports-matrix = <0 2 5 + 1 3 6 + 2 0 0xff + 3 1 0xff>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index e3fd148d462e..b746684f3fd3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14235,6 +14235,12 @@ L: linux-serial@vger.kernel.org S: Maintained F: drivers/tty/serial/8250/8250_pci1xxxx.c +MICROCHIP PD692X0 PSE DRIVER +M: Kory Maincent <kory.maincent@bootlin.com> +L: netdev@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml + MICROCHIP POLARFIRE FPGA DRIVERS M: Conor Dooley <conor.dooley@microchip.com> R: Vladimir Georgiev <v.georgiev@metrotek.ru>
Add the PD692x0 I2C Power Sourcing Equipment controller device tree bindings documentation. Sponsored-by: Dent Project <dentproject@linuxfoundation.org> Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> --- Changes in v2: - Enhance ports-matrix description. - Replace additionalProperties by unevaluatedProperties. - Drop i2c suffix. --- .../bindings/net/pse-pd/microchip,pd692x0.yaml | 77 ++++++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 83 insertions(+)