From patchwork Tue Dec 12 00:51:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Chan X-Patchwork-Id: 13488256 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="WP7SBu98" Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC2ADA6 for ; Mon, 11 Dec 2023 16:51:45 -0800 (PST) Received: by mail-qk1-x736.google.com with SMTP id af79cd13be357-77f8308616eso37638885a.2 for ; Mon, 11 Dec 2023 16:51:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1702342305; x=1702947105; darn=vger.kernel.org; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=I/PK91kUO/CCAwjCt15o7px/ZKEUyN3JIcrH6rtuZho=; b=WP7SBu987YVrRk6W/R5eVPhyXcWQN5wHW/oMstdU8zF4qqnBZzmiHwMVniH0KyZezh ZgvWb95ZDlE+z+Jv7EDLpqvIFH1sqbUqcEhEe0nKEPTXa24UYr3lsMuV1EwkMQ8LdUTB mKbhXz6WeX/BFB3KlVxp7eiygwTFSHawxI4tA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702342305; x=1702947105; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=I/PK91kUO/CCAwjCt15o7px/ZKEUyN3JIcrH6rtuZho=; b=hjSopr8T8UWCCBnu5E9U3gSyjb17Ec/n4r/XNzFyxMt7wTm1ix/pGn24Lg/az61S/6 PKk405ali+JmPO0zNJwnH/YmuISn6HVPgg3x68g3vJARb2uBFl1TnbFRP85OqTBgwrpf LWmbxgmHPyaAOVFk0l+tjXU6UrP+pfjmttUIZKdjGCgjOcA3oAwj87y2MWwXyrIwjNis 2kLhs2tdwi4NPREK/KbSAFklE5Q+zacao1aLhwYsQnZxyShyZv118sE5BxFdcT02aNbn NWo1WkhGAcuZWc5Ae+0aHnEJDJvvID+OFNXgTZCkJii9yumAGDCMXN/mUaGnkcogDq3X 0PtA== X-Gm-Message-State: AOJu0Yx9hnm3p9PNlCiYk/ivD6QW3H1DoHShnzkL7gvAw3IAd0P3AYoL S49g+gGx/x75Bwk7NH4xu+MLfFZ42Cvm+fMYsag= X-Google-Smtp-Source: AGHT+IF41m66EyCBuStgRbd7mlaXNngkMhu3Uusk/Y/tWOFx40rqknxXtvpHNPZMhRBWtGDQED9IGQ== X-Received: by 2002:a05:622a:341:b0:425:a60b:4d94 with SMTP id r1-20020a05622a034100b00425a60b4d94mr8482836qtw.21.1702342304734; Mon, 11 Dec 2023 16:51:44 -0800 (PST) Received: from lvnvda5233.lvn.broadcom.net ([192.19.161.250]) by smtp.gmail.com with ESMTPSA id r5-20020ac87945000000b00423ea1b31b3sm3619664qtt.66.2023.12.11.16.51.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Dec 2023 16:51:44 -0800 (PST) From: Michael Chan To: davem@davemloft.net Cc: netdev@vger.kernel.org, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, gospo@broadcom.com, Pavan Chebbi Subject: [PATCH net-next 01/13] bnxt_en: Fix trimming of P5 RX and TX rings Date: Mon, 11 Dec 2023 16:51:10 -0800 Message-Id: <20231212005122.2401-2-michael.chan@broadcom.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20231212005122.2401-1-michael.chan@broadcom.com> References: <20231212005122.2401-1-michael.chan@broadcom.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The recent commit to trim the RX and TX rings on P5 chips by assigning each with max CP rings divided by 2 is not correct. Max CP rings divided by 2 may be bigger than the original RX or TX and would lead to failure. In other words, we may be checking for increased RX/TX rings than required and it may fail. Fix it by calling __bnxt_trim_rings() instead that would properly trim RX and TX without the possibility of increasing their values. Fixes: f5b29c6afe36 ("bnxt_en: Add helper to get the number of CP rings required for TX rings") Reviewed-by: Pavan Chebbi Signed-off-by: Michael Chan --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index 92a54113f872..7afbbc71f92f 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -6489,6 +6489,8 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) } } +static int __bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, + bool shared); static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, bool shared); @@ -6532,8 +6534,9 @@ static int bnxt_hwrm_get_rings(struct bnxt *bp) if (bp->flags & BNXT_FLAG_AGG_RINGS) rx >>= 1; if (cp < (rx + tx)) { - rx = cp / 2; - tx = rx; + rc = __bnxt_trim_rings(bp, &rx, &tx, cp, false); + if (rc) + return rc; if (bp->flags & BNXT_FLAG_AGG_RINGS) rx <<= 1; hw_resc->resv_rx_rings = rx; @@ -13885,9 +13888,12 @@ static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, if (bp->flags & BNXT_FLAG_AGG_RINGS) *max_rx >>= 1; if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) { - if (*max_cp < (*max_rx + *max_tx)) { - *max_rx = *max_cp / 2; - *max_tx = *max_rx; + int rc; + + rc = __bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false); + if (rc) { + *max_rx = 0; + *max_tx = 0; } /* On P5 chips, max_cp output param should be available NQs */ *max_cp = max_irq;