@@ -340,6 +340,14 @@ static struct at803x_hw_stat qca83xx_hw_stats[] = {
};
enum {
+ APB_BRIDGE_CLK,
+ AHB_CLK,
+ SEC_CTRL_AHB_CLK,
+ TLMM_CLK,
+ TLMM_AHB_CLK,
+ CNOC_AHB_CLK,
+ MDIO_AHB_CLK,
+ MDIO_MASTER_AHB_CLK,
SRDS0_SYS_CLK,
SRDS1_SYS_CLK,
GEPHY0_SYS_CLK,
@@ -363,6 +371,14 @@ enum {
};
static const char *const qca8084_clock_name[] = {
+ "apb_bridge",
+ "ahb",
+ "sec_ctrl_ahb",
+ "tlmm",
+ "tlmm_ahb",
+ "cnoc_ahb",
+ "mdio_ahb",
+ "mdio_master_ahb",
"srds0_sys",
"srds1_sys",
"gephy0_sys",
@@ -975,6 +991,53 @@ static int qca8084_clock_config(struct phy_device *phydev)
return 0;
}
+static int qca8084_common_clock_init(struct phy_device *phydev)
+{
+ struct at803x_priv *priv;
+ int ret = 0;
+
+ priv = phydev->priv;
+ /* Enable APB bridge tree clock */
+ ret = clk_set_rate(priv->clk[APB_BRIDGE_CLK], 312500000);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk[APB_BRIDGE_CLK]);
+ if (ret)
+ return ret;
+
+ /* Enable AHB tree clocks */
+ ret = clk_set_rate(priv->clk[AHB_CLK], 104170000);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk[AHB_CLK]);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk[SEC_CTRL_AHB_CLK]);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk[TLMM_CLK]);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk[TLMM_AHB_CLK]);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk[CNOC_AHB_CLK]);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(priv->clk[MDIO_AHB_CLK]);
+ if (ret)
+ return ret;
+
+ return clk_prepare_enable(priv->clk[MDIO_MASTER_AHB_CLK]);
+}
+
static int qca8084_probe(struct phy_device *phydev)
{
int ret;
@@ -987,7 +1050,11 @@ static int qca8084_probe(struct phy_device *phydev)
if (ret)
return ret;
- return qca8084_clock_config(phydev);
+ ret = qca8084_clock_config(phydev);
+ if (ret)
+ return ret;
+
+ return qca8084_common_clock_init(phydev);
}
static int at803x_probe(struct phy_device *phydev)
After initial clock sequence, the clock source 312.5MHZ is available, the common clocks based on clock source 312.5MHZ needs to be configured, which includes APB bridge clock tree with rate 312.5MHZ, AHB clock tree with 104.17MHZ. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- drivers/net/phy/at803x.c | 69 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-)