diff mbox series

[v8,07/14] net: phy: at803x: add the possible_interfaces

Message ID 20231215074005.26976-8-quic_luoj@quicinc.com (mailing list archive)
State Changes Requested
Delegated to: Netdev Maintainers
Headers show
Series add qca8084 ethernet phy driver | expand

Checks

Context Check Description
netdev/tree_selection success Guessed tree name to be net-next
netdev/apply fail Patch does not apply to net-next

Commit Message

Jie Luo Dec. 15, 2023, 7:39 a.m. UTC 
When qca808x works on the interface mode sgmii or
2500base-x, the interface mode can be switched according
to the PHY link speed.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/at803x.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index bb382089ab77..cd1bdb61d122 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -2179,10 +2179,22 @@  static void qca808x_link_change_notify(struct phy_device *phydev)
 			QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
 }
 
+static void qca808x_fill_possible_interfaces(struct phy_device *phydev)
+{
+	unsigned long *possible = phydev->possible_interfaces;
+
+	if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII) {
+		__set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
+		__set_bit(PHY_INTERFACE_MODE_SGMII, possible);
+	}
+}
+
 static int qca8084_config_init(struct phy_device *phydev)
 {
 	int ret;
 
+	qca808x_fill_possible_interfaces(phydev);
+
 	/* Invert ADC clock edge */
 	ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL,
 				    QCA8084_ADC_CLK_SEL_ACLK,