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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VO1rTYwcWJiG7hByMXRMJ1hKv+ZW7ATUvOB7zJ5HfSrhTowaXrc2+N+6U671BLALih71gQ69xlD/6tT6eINYvnT1OP2aO99HFT62N1ruJy8P6cqcWcsGwQOAvuO4RQ3zdtXQiwr8//8bsPwnfh2W3aOS2C/QWpvT62axQRCTZyCGfYQRuUVwLb80uXdnXcPiZurDYP9yA2ljos4+14z3b8/c+BqSXkWSkbaB7lPOieS/aWl9pUvv2z88MkCOaxHCQc+7/3UKUktzQ4/3TxPui4D69kyR32V5cqzi6DWfaT1JhenysU9MLODPHWIJSCVzWi2uZluzx5P6qPQwJsyqN1Gov7VUlqaeq7wjuVdXSrvsEZ45Jdli7pcUfM+AyLHKhDUwty2ltv0aN4oKjUWv1bvPYsfG8O/f91X0HFFnRSaGjX2J32EYveTi9CA8obej24xs/Ap+woxl9JlJ8zcC/mPJNuEdVLnCk65o5b8GPGp55/WogcgF5tgMItX5FQ60RWRI90wZMOKla0kflfB6Z2zfhHxOMvzrIue20Gf7wc4xMUSUmz2NpKwkk4IK53bfkcYTke74cyWb7QzOyk0dbmf2AG5JTBmnqGRCx2INgg9yQBCVFKwZH+PxSiCEQNabiJZqv2hNr0cBxrtFAMqlHpd0V5lfZgVzrUvb+hei6TWwx/Oy5blAGxnmZboIHBoL1I7FSNBF3vILyLEl9a4fmlWbykr+Z2CVl5DJ6D5Y6sgK9zuvkhhJKsZw8eDvLPkO+JJsc54JcJGMFZKgCTwaH5tt3w9ZshIFyg0WrXmy3VVgOS/yxFTegEqU/9Vkj3oudeE5dn5KmHvBAX94x3yH5MD2MFbn5AhEAfcZNMAnPk9znJzMTuyCdQIEwoeQP5oICrUaMBHVQhHTexSIdGvknAM1XSutPQHI1J93UQk2bMikgidfedk9akkthSp0mdvXMNVS9995jCiUsOIMQJQgV0YJ4NRa8LfCoJd8eBFLSeeiDCCkPUW9MrDicplrA0W27dTt1oWegP1Y+8fdBDh8wgdZaejjG9KvxMv6+ZYgJWUfv5droMq+W9kCKY36MV6s0gHINPQzRzw4bmj/mY7CSyUYtBwOl+rA+D/M13C87ZvqCyqHYEnMa5QyjKePnK2FLfrvgtkXkkiFANNumwKJSwem0wxPM435otJWX8L/6/2rloVNJgOUD9yAPsicBKJ40BdyObHw/D1Cqcl+Rg1gBXWgcWXxVgl39J3z3UbLUABYVn7BNGD4Mm4VgkjlkJ3dC83FgAfy9Y0WvFIzbe3vTjzrJ2rXEyQVATikVu22W5hgccS05ZzwTDK/l8MZmb4jEGkok1Zr5pbUKDqJn8X3fRJQgXA3CNvSIkJKS7YkDfdjya9ZVDhkqPSPS8fbnV8zMgXGwdd30rCdSFhLaQ7051Iu24UwmkokufjQOjxWS7941Rp5Yktn2tRsLXt6CSOzktlrBz4Lqo8ckGxqVr+MtGpxWqqGsxrc3AyXzRC9JnYZONCK9wGnWmN62Zu2IFcRDKhsWQKpLcPjNLfnwisrpn0R33UNR56inBWyoJBzwEci9pbeaRkROjtOQpd11v3q X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1b988af1-2fd9-4759-2af6-08dc026ca2db X-MS-Exchange-CrossTenant-AuthSource: SJ1PR12MB6075.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2023 21:34:39.3069 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 87t+zdniny7nArJm1hVmiFXLYDD+Z0JtglXE78++W7G1VlLHr7Qgr0/66jHYVuLRgJLQUE2ohdJSA7/OewrsZg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7481 From: Yoray Zack Enable rx side of DDGST offload when supported. At the end of the capsule, check if all the skb bits are on, and if not recalculate the DDGST in SW and check it. Signed-off-by: Yoray Zack Signed-off-by: Boris Pismenny Signed-off-by: Ben Ben-Ishay Signed-off-by: Or Gerlitz Signed-off-by: Shai Malin Signed-off-by: Aurelien Aptel Reviewed-by: Chaitanya Kulkarni Reviewed-by: Max Gurtovoy --- drivers/nvme/host/tcp.c | 80 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 75 insertions(+), 5 deletions(-) diff --git a/drivers/nvme/host/tcp.c b/drivers/nvme/host/tcp.c index 420b8be309a4..6eed24b5f90c 100644 --- a/drivers/nvme/host/tcp.c +++ b/drivers/nvme/host/tcp.c @@ -143,6 +143,7 @@ enum nvme_tcp_queue_flags { NVME_TCP_Q_LIVE = 1, NVME_TCP_Q_POLLING = 2, NVME_TCP_Q_OFF_DDP = 3, + NVME_TCP_Q_OFF_DDGST_RX = 4, }; enum nvme_tcp_recv_state { @@ -180,6 +181,7 @@ struct nvme_tcp_queue { * is pending (ULP_DDP_RESYNC_PENDING). */ atomic64_t resync_tcp_seq; + bool ddp_ddgst_valid; #endif /* send state */ @@ -379,6 +381,30 @@ nvme_tcp_get_ddp_netdev_with_limits(struct nvme_tcp_ctrl *ctrl) return NULL; } +static inline bool nvme_tcp_ddp_ddgst_ok(struct nvme_tcp_queue *queue) +{ + return queue->ddp_ddgst_valid; +} + +static inline void nvme_tcp_ddp_ddgst_update(struct nvme_tcp_queue *queue, + struct sk_buff *skb) +{ + if (queue->ddp_ddgst_valid) + queue->ddp_ddgst_valid = skb_is_ulp_crc(skb); +} + +static void nvme_tcp_ddp_ddgst_recalc(struct ahash_request *hash, + struct request *rq, + __le32 *ddgst) +{ + struct nvme_tcp_request *req; + + req = blk_mq_rq_to_pdu(rq); + ahash_request_set_crypt(hash, req->ddp.sg_table.sgl, (u8 *)ddgst, + req->data_len); + crypto_ahash_digest(hash); +} + static bool nvme_tcp_resync_request(struct sock *sk, u32 seq, u32 flags); static void nvme_tcp_ddp_teardown_done(void *ddp_ctx); static const struct ulp_ddp_ulp_ops nvme_tcp_ddp_ulp_ops = { @@ -468,6 +494,10 @@ static int nvme_tcp_offload_socket(struct nvme_tcp_queue *queue) return ret; set_bit(NVME_TCP_Q_OFF_DDP, &queue->flags); + if (queue->data_digest && + ulp_ddp_is_cap_active(queue->ctrl->ddp_netdev, + ULP_DDP_CAP_NVME_TCP_DDGST_RX)) + set_bit(NVME_TCP_Q_OFF_DDGST_RX, &queue->flags); return 0; } @@ -475,6 +505,7 @@ static int nvme_tcp_offload_socket(struct nvme_tcp_queue *queue) static void nvme_tcp_unoffload_socket(struct nvme_tcp_queue *queue) { clear_bit(NVME_TCP_Q_OFF_DDP, &queue->flags); + clear_bit(NVME_TCP_Q_OFF_DDGST_RX, &queue->flags); ulp_ddp_sk_del(queue->ctrl->ddp_netdev, queue->sock->sk); } @@ -583,6 +614,20 @@ static void nvme_tcp_resync_response(struct nvme_tcp_queue *queue, struct sk_buff *skb, unsigned int offset) {} +static inline bool nvme_tcp_ddp_ddgst_ok(struct nvme_tcp_queue *queue) +{ + return false; +} + +static inline void nvme_tcp_ddp_ddgst_update(struct nvme_tcp_queue *queue, + struct sk_buff *skb) +{} + +static void nvme_tcp_ddp_ddgst_recalc(struct ahash_request *hash, + struct request *rq, + __le32 *ddgst) +{} + #endif static void nvme_tcp_init_iter(struct nvme_tcp_request *req, @@ -843,6 +888,9 @@ static void nvme_tcp_init_recv_ctx(struct nvme_tcp_queue *queue) queue->pdu_offset = 0; queue->data_remaining = -1; queue->ddgst_remaining = 0; +#ifdef CONFIG_ULP_DDP + queue->ddp_ddgst_valid = true; +#endif } static void nvme_tcp_error_recovery(struct nvme_ctrl *ctrl) @@ -1108,6 +1156,9 @@ static int nvme_tcp_recv_data(struct nvme_tcp_queue *queue, struct sk_buff *skb, nvme_cid_to_rq(nvme_tcp_tagset(queue), pdu->command_id); struct nvme_tcp_request *req = blk_mq_rq_to_pdu(rq); + if (test_bit(NVME_TCP_Q_OFF_DDGST_RX, &queue->flags)) + nvme_tcp_ddp_ddgst_update(queue, skb); + while (true) { int recv_len, ret; @@ -1136,7 +1187,8 @@ static int nvme_tcp_recv_data(struct nvme_tcp_queue *queue, struct sk_buff *skb, recv_len = min_t(size_t, recv_len, iov_iter_count(&req->iter)); - if (queue->data_digest) + if (queue->data_digest && + !test_bit(NVME_TCP_Q_OFF_DDGST_RX, &queue->flags)) ret = skb_copy_and_hash_datagram_iter(skb, *offset, &req->iter, recv_len, queue->rcv_hash); else @@ -1178,8 +1230,11 @@ static int nvme_tcp_recv_ddgst(struct nvme_tcp_queue *queue, char *ddgst = (char *)&queue->recv_ddgst; size_t recv_len = min_t(size_t, *len, queue->ddgst_remaining); off_t off = NVME_TCP_DIGEST_LENGTH - queue->ddgst_remaining; + struct request *rq; int ret; + if (test_bit(NVME_TCP_Q_OFF_DDGST_RX, &queue->flags)) + nvme_tcp_ddp_ddgst_update(queue, skb); ret = skb_copy_bits(skb, *offset, &ddgst[off], recv_len); if (unlikely(ret)) return ret; @@ -1190,9 +1245,25 @@ static int nvme_tcp_recv_ddgst(struct nvme_tcp_queue *queue, if (queue->ddgst_remaining) return 0; + rq = nvme_cid_to_rq(nvme_tcp_tagset(queue), + pdu->command_id); + + if (test_bit(NVME_TCP_Q_OFF_DDGST_RX, &queue->flags)) { + /* + * If HW successfully offloaded the digest + * verification, we can skip it + */ + if (nvme_tcp_ddp_ddgst_ok(queue)) + goto out; + /* + * Otherwise we have to recalculate and verify the + * digest with the software-fallback + */ + nvme_tcp_ddp_ddgst_recalc(queue->rcv_hash, rq, + &queue->exp_ddgst); + } + if (queue->recv_ddgst != queue->exp_ddgst) { - struct request *rq = nvme_cid_to_rq(nvme_tcp_tagset(queue), - pdu->command_id); struct nvme_tcp_request *req = blk_mq_rq_to_pdu(rq); req->status = cpu_to_le16(NVME_SC_DATA_XFER_ERROR); @@ -1203,9 +1274,8 @@ static int nvme_tcp_recv_ddgst(struct nvme_tcp_queue *queue, le32_to_cpu(queue->exp_ddgst)); } +out: if (pdu->hdr.flags & NVME_TCP_F_DATA_SUCCESS) { - struct request *rq = nvme_cid_to_rq(nvme_tcp_tagset(queue), - pdu->command_id); struct nvme_tcp_request *req = blk_mq_rq_to_pdu(rq); nvme_tcp_end_request(rq, le16_to_cpu(req->status));