From patchwork Mon Jan 22 11:03:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabian Pfitzner X-Patchwork-Id: 13525203 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8D663EA65 for ; Mon, 22 Jan 2024 11:04:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705921486; cv=none; b=WJJZZ6dl+fVMGsKLSCcRLBWsNK20yNje3VcWDsbK37SlucfmjIe62yBPR9Jw7cuXaKc2OYV61ZFP+lJ4laJm3pKQle5LW+p/ppvdcY2Muz8OrzUF2C/J7DPyWP8jZ9S0ludck9NwtsfgEJvTDKyG8Rb9skV4i9RslkXjjEm0oKw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705921486; c=relaxed/simple; bh=eqirOGjCZP2NBSEkK8uc5P/vksk2IIWKQWYB/n+5qkY=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=iVMwcgbAO8UTJ5XxlVwdJTDV4RRdsg1roJ/jI2lNXnmFAy1cXB4G1sL14uaLVFQelJgMXUNuaMZRwWOwtfCkou2SMmaEoSX2jBRfBOhnXRSnNK8S0hmdtA+6OHqihRWh+17QlO8nwbvmoJ71yFfD/ysqoNbix0sh/xObHSDEO4Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rRs6K-0003nV-7r; Mon, 22 Jan 2024 12:04:24 +0100 Received: from [2a0a:edc0:0:1101:1d::54] (helo=dude05.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rRs6I-001Zhh-Mi; Mon, 22 Jan 2024 12:04:22 +0100 Received: from fpf by dude05.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1rRs6I-00BSQd-23; Mon, 22 Jan 2024 12:04:22 +0100 From: Fabian Pfitzner To: Michael Hennerich , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King , Alexandru Tachici Cc: kernel@pengutronix.de, Fabian Pfitzner , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] net: phy: adin: add missing clock option Date: Mon, 22 Jan 2024 12:03:12 +0100 Message-Id: <20240122110311.2725036-1-f.pfitzner@pengutronix.de> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: fpf@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The GP_CLK pin on Adin1300 PHY's offers three different output clocks. This patch adds the missing 125MHz recovered clock option which is not yet availible in the driver. Signed-off-by: Fabian Pfitzner --- Documentation/devicetree/bindings/net/adi,adin.yaml | 7 +++++-- drivers/net/phy/adin.c | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml index 929cf8c0b0fd..cd1b4efa692b 100644 --- a/Documentation/devicetree/bindings/net/adi,adin.yaml +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml @@ -38,14 +38,17 @@ properties: adi,phy-output-clock: description: | - Select clock output on GP_CLK pin. Two clocks are available: - A 25MHz reference and a free-running 125MHz. + Select clock output on GP_CLK pin. Three clocks are available: + - 25MHz reference + - free-running 125MHz + - recovered 125MHz The phy can alternatively automatically switch between the reference and the 125MHz clocks based on its internal state. $ref: /schemas/types.yaml#/definitions/string enum: - 25mhz-reference - 125mhz-free-running + - 125mhz-recovered - adaptive-free-running adi,phy-output-reference-clock: diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index 2e1a46e121d9..b1ed6fd24763 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -508,6 +508,8 @@ static int adin_config_clk_out(struct phy_device *phydev) sel |= ADIN1300_GE_CLK_CFG_25; } else if (strcmp(val, "125mhz-free-running") == 0) { sel |= ADIN1300_GE_CLK_CFG_FREE_125; + } else if (strcmp(val, "125mhz-recovered") == 0) { + sel |= ADIN1300_GE_CLK_CFG_RCVR_125; } else if (strcmp(val, "adaptive-free-running") == 0) { sel |= ADIN1300_GE_CLK_CFG_HRT_FREE; } else {