From patchwork Tue Feb 20 23:57:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinicius Costa Gomes X-Patchwork-Id: 13564770 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA19F154C0D; Tue, 20 Feb 2024 23:57:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708473444; cv=none; b=Hxt/knmkq8jmzFI9+rLSPFPTJw+HzyypJK0mxnW1jy46YumwCw1I4gnjp3Gc1yJPMq3HnXSUlV42AyKy5omVOu4x+HKTTFlempNb3lwOzCbS+zxaJj7awiQHqbgmKWlEBYwquq+iUvxy37ROAay7qE0ajXjRBiU35VPoAv4vg9c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708473444; c=relaxed/simple; bh=ndy7ThxenZxil/rvXJUUjRiW8Z85XoIMMBuihvffwjI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dYpar9oCtFkg9xZ3fDtSjHcec/1jjmguXuiatAG3u6ykbkmjYRXd57KN4W+dpHPHxuebDMGNJJr7E+ZLpppYfD1+5byyIST9Pw+bRJrFy2R5+3uQshzC9iSY+QURs7yEP9xNZJYPLGPrKi8cqvR83XVBy9dqCBToz5TZQljgksk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gVgTiCQN; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gVgTiCQN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708473443; x=1740009443; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ndy7ThxenZxil/rvXJUUjRiW8Z85XoIMMBuihvffwjI=; b=gVgTiCQN7SrRXeD9PQN75+b5mH290SDP73GUFur0S42kV6CPGS1MtLKq 995MGHrxG7GiXcrdEXGycbl4DwdsCODAkVST1ll1RQXCL7ePJvu82CYIY ZTDsBtpnH/mni7d2yDjocQP2iQbO7AMoKDP5yaQFywGHmIlZDqvjec6YN tF+0oxRFcWD/E7DjQt7DctmdLaXobuG3+lzNKRLk0boBqka5BPVchMjfs eirlYTH0ogmZaQ1IOZIfcgueH3qsOFgtGgViGTpo7G32iYYgoQKwKsL5R tzx6elb9reSkidTKeJgRFrtg9yEPhmuQuOMD+iHbS8VhBdI9/+wJJvUdm w==; X-IronPort-AV: E=McAfee;i="6600,9927,10990"; a="20041763" X-IronPort-AV: E=Sophos;i="6.06,174,1705392000"; d="scan'208";a="20041763" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 15:57:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,174,1705392000"; d="scan'208";a="5092387" Received: from vcostago-mobl3.jf.intel.com ([10.24.14.83]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 15:57:19 -0800 From: Vinicius Costa Gomes To: intel-wired-lan@lists.osuosl.org Cc: sasha.neftin@intel.com, richardcochran@gmail.com, kurt@linutronix.de, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, netdev@vger.kernel.org, Vinicius Costa Gomes , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jeff Kirsher , linux-kernel@vger.kernel.org Subject: [iwl-net v2 1/2] igc: Fix missing time sync events Date: Tue, 20 Feb 2024 15:57:10 -0800 Message-ID: <20240220235712.241552-2-vinicius.gomes@intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240220235712.241552-1-vinicius.gomes@intel.com> References: <20240220235712.241552-1-vinicius.gomes@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Fix "double" clearing of interrupts, which can cause external events or timestamps to be missed. The IGC_TSIRC Time Sync Interrupt Cause register can be cleared in two ways, by either reading it or by writing '1' into the specific cause bit. This is documented in section 8.16.1. The following flow was used: 1. read IGC_TSIRC into 'tsicr'; 2. handle the interrupts present in 'tsirc' and mark them in 'ack'; 3. write 'ack' into IGC_TSICR; As both (1) and (3) will clear the interrupt cause, if the same interrupt happens again between (1) and (3) it will be ignored, causing events to be missed. Remove the extra clear in (3). Fixes: 2c344ae24501 ("igc: Add support for TX timestamping") Reviewed-by: Kurt Kanzenbach Tested-by: Kurt Kanzenbach # Intel i225 Signed-off-by: Vinicius Costa Gomes Tested-by: Naama Meir --- drivers/net/ethernet/intel/igc/igc_main.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index ba8d3fe186ae..39b6a8d64de3 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -5302,25 +5302,22 @@ igc_features_check(struct sk_buff *skb, struct net_device *dev, static void igc_tsync_interrupt(struct igc_adapter *adapter) { - u32 ack, tsauxc, sec, nsec, tsicr; struct igc_hw *hw = &adapter->hw; + u32 tsauxc, sec, nsec, tsicr; struct ptp_clock_event event; struct timespec64 ts; tsicr = rd32(IGC_TSICR); - ack = 0; if (tsicr & IGC_TSICR_SYS_WRAP) { event.type = PTP_CLOCK_PPS; if (adapter->ptp_caps.pps) ptp_clock_event(adapter->ptp_clock, &event); - ack |= IGC_TSICR_SYS_WRAP; } if (tsicr & IGC_TSICR_TXTS) { /* retrieve hardware timestamp */ igc_ptp_tx_tstamp_event(adapter); - ack |= IGC_TSICR_TXTS; } if (tsicr & IGC_TSICR_TT0) { @@ -5334,7 +5331,6 @@ static void igc_tsync_interrupt(struct igc_adapter *adapter) wr32(IGC_TSAUXC, tsauxc); adapter->perout[0].start = ts; spin_unlock(&adapter->tmreg_lock); - ack |= IGC_TSICR_TT0; } if (tsicr & IGC_TSICR_TT1) { @@ -5348,7 +5344,6 @@ static void igc_tsync_interrupt(struct igc_adapter *adapter) wr32(IGC_TSAUXC, tsauxc); adapter->perout[1].start = ts; spin_unlock(&adapter->tmreg_lock); - ack |= IGC_TSICR_TT1; } if (tsicr & IGC_TSICR_AUTT0) { @@ -5358,7 +5353,6 @@ static void igc_tsync_interrupt(struct igc_adapter *adapter) event.index = 0; event.timestamp = sec * NSEC_PER_SEC + nsec; ptp_clock_event(adapter->ptp_clock, &event); - ack |= IGC_TSICR_AUTT0; } if (tsicr & IGC_TSICR_AUTT1) { @@ -5368,11 +5362,7 @@ static void igc_tsync_interrupt(struct igc_adapter *adapter) event.index = 1; event.timestamp = sec * NSEC_PER_SEC + nsec; ptp_clock_event(adapter->ptp_clock, &event); - ack |= IGC_TSICR_AUTT1; } - - /* acknowledge the interrupts */ - wr32(IGC_TSICR, ack); } /**