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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?7ugf6/TXxOz1g+69D0x9Ft7HN2R6?= =?utf-8?q?Dr/ala8P46IzZ630vPA+bDkCQqTj8U6uD+Irazg0u4ozgze6s95BSng1iHUowQEp3?= =?utf-8?q?fnOBFuJoP6tHIxjTwxvvdp5f0fAahmKN2WrkcgQhQpaaEpAy7FZTInwTbQD8ENXu8?= =?utf-8?q?NZm4qwa6aVNHgb/HZQp0lpgQsVMnJUpm6UncFgN/BMOQr6LQIhtbGie1xn2isaCPc?= =?utf-8?q?aH/OjPCpZBhkRJR1YjSkD0YdH/K/AEuObeV/OG0iNBC/Z+e2KDddf+dWmnYndsWzk?= =?utf-8?q?nyLAGQwrlOZqBTET00Wxm08vXbBQtsACU2Jq3c3bCRB+423h38KW1XV14+zKQ51sm?= =?utf-8?q?XevVe60XBztQ7RdqYg+uJKrH6AFsuEKoDeEqETP+1bFkuWxeEPaiRmQuR4YT3i+Tz?= =?utf-8?q?SBJVgGqh6fMf8Ot8Nyjc+8WRETMlO6qIAFWeru2QkDGOOGjmwFc9z7/oMD/2WImXc?= =?utf-8?q?YTi3eaUflrphhicP0p/ZnSyLREwVmX82zsQSbEmKqcyhXYRtlhK2yWR2zoc8W9Fwo?= =?utf-8?q?7PfoUI4tE4Hzr4nMRQQcmhCGRHMrRQAypCKXJNWK37C8LAzPIwgRVEx4t3X1kw736?= =?utf-8?q?VLAt75TtGPu+gEr9OYF2jV9WHrMUwLxYMXgiYMpYXXT0pV4h/iCXP11viWW69L2Xp?= =?utf-8?q?+ecoACrHeQzq5pREIIca8OfJP8qZWTs/m+ZKiAULabmSqBqKMEsMOLrousJpwXs9d?= =?utf-8?q?tfGbceT6UfM92Do38x1+H7Oahv2I188TG5eNzAemIDSXehLVo4BMTfr0kJWQr84g5?= =?utf-8?q?eimuW+cJb6aC/KGaLR4Odf09lhntwNdJPuaiKymdrrHv6W8vzjplxmPPwCWBBL+H+?= =?utf-8?q?U45d75v4xn4zk6Psdur+8VTTqWRyL2eTGw1r62B8veMAnY7ky6ffSNpdegXbmHFtp?= =?utf-8?q?zA5Rze/LAY5odNJe1mkhn3+Zp2Z3SD13Ceu8ryBoE/VV0gyMuHQEh3sFy19yau6Hx?= =?utf-8?q?nzH/FgaicDyFjI2CS5yp5KaZsGmsRGo9wtGP7jIomm4fWk1d+B93FDxX1MKMg6Tnw?= =?utf-8?q?SM8kdBGxAEwnFJf+weOusfWwRb7cvMA4GC5WaWnJX8lwvgTcCDDICNKf2vFS2prHb?= =?utf-8?q?OO+bmHPYbjNXw2EtH/ky3dkUFNIwiy/9EOdrvXcZeB3Z3pCC71gL0bsoQp5flLaEH?= =?utf-8?q?fiIH1ogS1ixVJsC53ApRNlcZ3QhVltlZaobYmmxTLXErPW+nyKURgNTfYz5BEupD5?= =?utf-8?q?vpcveU39C2ohxZh9ifiQWGmbBR5+mxcKsS+KyJ5qeyExCFcEZ6C7GmxB4XpxE/sWd?= =?utf-8?q?w+iOjcdKUCMpVcsL9gSqEANoFuqzWeUpxIhmxFXbDhwam8yddkUww5Fw4NVYHE6a9?= =?utf-8?q?Fo6Q1TVvcPApR2kLtsJeCVNn4JI9L0vblLNCtmQ7nJp5Xpj2uvdfp5Crfc0W9QynP?= =?utf-8?q?Bz1nN11aVIMKVC6kyM8HIh1O21ejps3A0B/797TnZ1Qy3IQtQ7NSxZ8r+UPfL0GYF?= =?utf-8?q?n46w8IcO4M0nZTfx3o40Gp7JfFNr7xP8zPvVo66dPCfvfy8qpIDxaXoGXMxwECpPf?= =?utf-8?q?aC6YiXlqUvfW?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6c6e0f52-be8a-4979-e4e7-08dc37ddbf4d X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2024 21:47:51.8577 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: yF5Z3jUtvkv/pyu5AlzpUOzfLP6AjMvO+lIv6sRZCxTPsK7I5pZyBHjYU6FClVa0TgI951kzxJ1U/td2tDhjvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7056 Instead of using the switch case statement to enable/disable the reference clock handled by this driver itself, let's introduce a new callback set_ref_clk() and define it for platforms that require it. This simplifies the code. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx.c | 119 ++++++++++++++++------------------- 1 file changed, 55 insertions(+), 64 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx.c b/drivers/pci/controller/dwc/pci-imx.c index e646ad70a2a5e..a63ce171ede8f 100644 --- a/drivers/pci/controller/dwc/pci-imx.c +++ b/drivers/pci/controller/dwc/pci-imx.c @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); }; struct imx_pcie { @@ -585,77 +586,54 @@ static int imx_pcie_attach_pd(struct device *dev) return 0; } -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - unsigned int offset; - int ret = 0; + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); - break; - case IMX6QP: - case IMX6Q: + return 0; +} + +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) +{ + if (enable) { /* power up core phy and enable ref clock */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); /* - * the async reset input need ref clock to sync internally, - * when the ref clock comes after reset, internal synced - * reset time is too short, cannot meet the requirement. - * add one ~10us delay here. + * the async reset input need ref clock to sync internally, when the ref clock comes + * after reset, internal synced reset time is too short, cannot meet the + * requirement.add one ~10us delay here. */ usleep_range(10, 100); regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); - break; - case IMX7D: - case IMX95: - case IMX95_EP: - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - offset = imx_pcie_grp_offset(imx_pcie); - /* - * Set the over ride low and enabled - * make sure that REF_CLK is turned on. - */ - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, - 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); - break; + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN); + } else { + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); } - return ret; + return 0; } -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - switch (imx_pcie->drvdata->variant) { - case IMX6QP: - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, - IMX6Q_GPR1_PCIE_TEST_PD); - break; - case IMX7D: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); - break; - default: - break; - } + int offset = imx_pcie_grp_offset(imx_pcie); + + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/ + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); + return 0; +} + +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); + return 0; } static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) @@ -668,10 +646,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) if (ret) return ret; - ret = imx_pcie_enable_ref_clk(imx_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie ref clock\n"); - goto err_ref_clk; + if (imx_pcie->drvdata->set_ref_clk) { + ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true); + if (ret) { + dev_err(dev, "unable to enable pcie ref clock\n"); + goto err_ref_clk; + } } /* allow the clocks to stabilize */ @@ -686,7 +666,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) { - imx_pcie_disable_ref_clk(imx_pcie); + if (imx_pcie->drvdata->set_ref_clk) + imx_pcie->drvdata->set_ref_clk(imx_pcie, false); clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } @@ -1462,6 +1443,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, + .set_ref_clk = imx6q_pcie_set_ref_clk, }, [IMX6SX] = { .variant = IMX6SX, @@ -1476,6 +1458,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, + .set_ref_clk = imx6sx_pcie_set_ref_clk, }, [IMX6QP] = { .variant = IMX6QP, @@ -1491,6 +1474,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, + .set_ref_clk = imx6q_pcie_set_ref_clk, }, [IMX7D] = { .variant = IMX7D, @@ -1503,6 +1487,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, + .set_ref_clk = imx7d_pcie_set_ref_clk, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1516,6 +1501,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .init_phy = imx8mq_pcie_init_phy, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MM] = { .variant = IMX8MM, @@ -1527,6 +1513,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx8mm_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MP] = { .variant = IMX8MP, @@ -1538,6 +1525,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx8mm_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX95] = { .variant = IMX95, @@ -1564,6 +1552,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, .init_phy = imx8mq_pcie_init_phy, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, @@ -1575,6 +1564,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1586,6 +1576,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX95_EP] = { .variant = IMX95_EP,