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Miller" , "Nabil S . Alramli" , Joe Damato , Rahul Rameshbabu Subject: [PATCH RFC 4/6] net/mlx5e: Introduce per-channel coalescing parameters with global coalescing support Date: Wed, 6 Mar 2024 15:04:20 -0800 Message-ID: <20240306230439.647123-5-rrameshbabu@nvidia.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240306230439.647123-1-rrameshbabu@nvidia.com> References: <20240306230439.647123-1-rrameshbabu@nvidia.com> X-ClientProxiedBy: SJ0PR03CA0104.namprd03.prod.outlook.com (2603:10b6:a03:333::19) To BYAPR12MB2743.namprd12.prod.outlook.com (2603:10b6:a03:61::28) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR12MB2743:EE_|DS0PR12MB8317:EE_ X-MS-Office365-Filtering-Correlation-Id: 971bf5e8-0ab6-4efa-94cb-08dc3e31d1a2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6bbs/WmXAALhDUeswqzqPZjiNzAGTMs0hFmntjYQdru2MG7XR9R+ZS1G8oeDCGERhLfs728AApln+3CPOXhwWaN8H/GGbPmO33J4gN8lndxrEVm/mX/ploOZ5lbpQn1lp25SsVHoiaaecBIhtPrC1ZMuig6nAHCU1u0b2OrGQIIt3UboLa2Ou/2Gxl4u7ipQFb6n/GIVIHUK+dAHPfpWXszDq8spGvKvys6cf3Y/Wk1+IfJsNX4GiVi8cc13YWrumQX8O8x+89uqG3FVapVJuw5Bp9R/iE0p4tJzdR7tu1fXeBWIJhILdSw1o3ekgRWea1kRps7wCcIT3k2QHkBRzByKVxaBsRRw2UJ30yFNGwAJqJlhX9Tk8SoAqmwYaK/BVwnqtocTtNZIEkFOa0lJB30XnwubrkqnEF7BiVq1pMmeXo2cg4NpLHDES/jhmvSmDyMugU9KWTlefORjqKcgt1XWUmOXcgTTe1v8k7LkAaGFno3cSjZcDMeshXg6e802zMVsbgoqHknim+weyJqMjY+M0oSEk3p6baZtegZ3KNg2wPjzxXfP1PWMusDmj2/pwzYseey3o5MVWjOjfwgT3QUKOe1UgDymFGn9BTlixe5OKoArN5M0jnB6Q9Scs07/RbK0m0u2x+rAaL0Jrh8F5BD9n1I78WwaYSLb84/BvWk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BYAPR12MB2743.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: I28dmqEGjX0lPzfsZazCSMKQm6pKMLJ0sXG+hEGUdYhyKbAFhKAkRxw2oet/meqzg3yIrRTJ7wFlmC/naT6oCehByI42S/t/IcwQnSz+L9X1DUfPpR+CpaOoJfAaGv24SCcjeNah8XFDU/MjRXcTHY6vUAi8ptxyJZ+29s9fjApafTyFMbUx9LooW2HyZ1ORFqDdD43KQbKGJHqzc9iXlSpSzS91tYa0P1fwXIXrfbS8571wh0lZDxSuBUM8AQhcqsVgw2RUHrj3KWPnrj2zubyDVUeGCOStf4TcQX3vjmWrPz2sy3+cREwIgzwp9lPDk2qOUf1/xuASWnI5VtjcZPo+Wu256889fIDJhD8G8tH8ppHCD79881hr0v6YBjWXO3sK4i9be6giaiy962HLeIbGbPmn/ZM6tbaH8jIUOP0iRgeV2KWdFSMcqAsYX9xiS5NkpZHiCxegjIp6n2+YO2N2FSsllNMBA/3fMQkpbAd+VHuWRrzhmuWmiwDi7vdT02Tif+aUnttOzq8l7N2Cx8fxaO33g+mOJFOFbl+MBPKUJ0ZPCh95ypWnJMBLQ6Hq2ZMaP3TyZx9egLDUM47US+iC46oAZxr46pumVmJlTCJAm1lsA/KwYlhcFfIs73mjKKPlWmnpqq0L1+t5G4KfMF54uIpdP1tcTrwJO18diT2FhyFAzK52l5fEfL5Jty9bPbEDSWRyNAs6K8eo02Bk5zq2Amg9scEcuJAQxe1b8409G4gLvL5BdhLc2kQms0FJkGOM+nRi5dA5k+FyjBK7EsQ8xPt3BSiRfCBsDlbiqilRiYstnZx5O5Mmgs8vjJ4+N5JE55UIbts1HOUkX90pPCsRlcFCVMfUwzrV4UO/lc9U0bLvUPUCxdYWvXlDxNOSpeTIH4YVTvls6mDftSC3EOtFkzH7SRZaay6f7b5vBDcY12ryklwtSTcPQDWZWeIMGyooy7Z+F9xn/ORohOCmrNeTqbGDnCzfTXmZPwavnaruNKS7b1oUkay/H3YYkhhZmUJERxJCvNpwWTxBHWyYrBl0beKNWWaYsSFmZrXIgkrgGxSQYAQ++Gai87k3G9LhxlepbNZ4jDFKwIUtra4rBxUxwwXJMSArjyMsxHJzMgdQLfQ4V4liPcFy3PBMRZWLlhZFhy14qW2Jm/ge1GZBER+TRIeSlaglSFvR6GDogiFY20uW4OETyFHjAMe7EqW2jjzZa0zPuSkB/S53m1mvM47hT+AYC7qcJ5PtYWsz+vjCgmRN3Z4KvodGEgSA13o3EKDlbcoIS+g3qfi9cJdI7G2zveqwKjsg64nEukfJ7yeRhunOqrHv29E8+4D/Vqo5YjliQva2ybxFCzzp45+Ks+NCgu2eeD6d/QJYOVnqmWIsphoEqf5AsCrTdsjuIu5WWR4hhcN8V4YUlbaxZS4PUipuWYMRe8rgVJzSY9f8+tXUFTInmsBjwOSZ27KMDx/Typ4ZnXCz95yfRnMaGUGJEhvr/e78xEu/yXzfrjvkg9FhjjSeAlXycYklq4y7Hc7//3+Cx4vLHiwBkH4zMniW1NJ7r7XIsX+JDehgF494OUsUiH7ImRwfMwfBxuZjfSgmigKR+xutOIpKof7ZFeQW5Q== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 971bf5e8-0ab6-4efa-94cb-08dc3e31d1a2 X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB2743.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2024 23:04:47.2227 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vl7R9DTyny7av2yBa1/RpkqtYnby42aFWCA+0CfKryu/iR/yk5XyH6K5ClgMS3ejIWhJ+9Q6/mXrS0RBZM7TQQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8317 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Enumerate per-channel coalescing parameters in the global coalescing reconfiguration path. Add other variables global use_cqe_mode trackers for Rx and Tx in order to support advertising the global CQE mode set while also supporting per-channel configuration. The goal is to prepare the driver to support per-channel coalescing configuration in downstream patches. Co-developed-by: Nabil S. Alramli Co-developed-by: Joe Damato Signed-off-by: Rahul Rameshbabu Reviewed-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 10 ++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index b6b7e02069b8..1ae0d4635d8a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -753,6 +753,12 @@ enum mlx5e_channel_state { MLX5E_CHANNEL_NUM_STATES }; +struct mlx5e_moder { + struct dim_cq_moder dim; + /* Consumed when dim is not enabled */ + struct ethtool_coalesce coal_params; +}; + struct mlx5e_channel { /* data path */ struct mlx5e_rq rq; @@ -794,6 +800,10 @@ struct mlx5e_channel { int cpu; /* Sync between icosq recovery and XSK enable/disable. */ struct mutex icosq_recovery_lock; + + /* coalescing configuration */ + struct mlx5e_moder rx_moder; + struct mlx5e_moder tx_moder; }; struct mlx5e_ptp; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 616bfab5b186..b601a7db9672 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -570,6 +570,7 @@ mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coal for (i = 0; i < priv->channels.num; ++i) { struct mlx5e_channel *c = priv->channels.c[i]; + c->tx_moder.coal_params = *coal; for (tc = 0; tc < c->num_tc; tc++) { mlx5_core_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq, @@ -588,6 +589,7 @@ mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct ethtool_coal for (i = 0; i < priv->channels.num; ++i) { struct mlx5e_channel *c = priv->channels.c[i]; + c->rx_moder.coal_params = *coal; mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, coal->rx_coalesce_usecs, coal->rx_max_coalesced_frames);