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Wed, 6 Mar 2024 15:13:00 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 6 Mar 2024 15:12:59 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Wed, 6 Mar 2024 15:12:57 -0800 From: William Tu To: CC: , , , , , Subject: [PATCH RFC v3 net-next 2/2] net/mlx5e: Add eswitch shared descriptor devlink Date: Thu, 7 Mar 2024 01:12:53 +0200 Message-ID: <20240306231253.8100-2-witu@nvidia.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20240306231253.8100-1-witu@nvidia.com> References: <20240306231253.8100-1-witu@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE32:EE_|DM6PR12MB4188:EE_ X-MS-Office365-Filtering-Correlation-Id: 47419444-407e-4ab2-6883-08dc3e32fd16 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This is used to configure the shared memory pool for eswitch. Signed-off-by: William Tu --- .../net/ethernet/mellanox/mlx5/core/devlink.c | 2 + .../net/ethernet/mellanox/mlx5/core/eswitch.h | 5 ++ .../mellanox/mlx5/core/eswitch_offloads.c | 49 +++++++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c index 3e064234f6fe..cc0c50691ecd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c @@ -312,6 +312,8 @@ static const struct devlink_ops mlx5_devlink_ops = { .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, + .eswitch_spool_size_set = mlx5_devlink_eswitch_spool_size_set, + .eswitch_spool_size_get = mlx5_devlink_eswitch_spool_size_get, .rate_leaf_tx_share_set = mlx5_esw_devlink_rate_leaf_tx_share_set, .rate_leaf_tx_max_set = mlx5_esw_devlink_rate_leaf_tx_max_set, .rate_node_tx_share_set = mlx5_esw_devlink_rate_node_tx_share_set, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index 349e28a6dd8d..2e2e3b5c3b3f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -378,6 +378,8 @@ struct mlx5_eswitch { struct mlx5_esw_functions esw_funcs; struct { u32 large_group_num; + u32 shared_rx_ring_counts; + bool enable_shared_rx_ring; } params; struct blocking_notifier_head n_head; struct xarray paired; @@ -549,6 +551,9 @@ int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, struct netlink_ext_ack *extack); int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, enum devlink_eswitch_encap_mode *encap); +int mlx5_devlink_eswitch_spool_size_set(struct devlink *devlink, u32 size, + struct netlink_ext_ack *extack); +int mlx5_devlink_eswitch_spool_size_get(struct devlink *devlink, u32 *size); int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port, u8 *hw_addr, int *hw_addr_len, struct netlink_ext_ack *extack); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index b0455134c98e..e27d9fba8840 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4019,6 +4019,55 @@ int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, return 0; } +int mlx5_devlink_eswitch_spool_size_set(struct devlink *devlink, + u32 spool_size, + struct netlink_ext_ack *extack) +{ + struct mlx5_eswitch *esw; + bool enable; + int err = 0; + int counts; + + esw = mlx5_devlink_eswitch_get(devlink); + if (IS_ERR(esw)) + return PTR_ERR(esw); + + down_write(&esw->mode_lock); + if (esw->mode == MLX5_ESWITCH_OFFLOADS) { + NL_SET_ERR_MSG_MOD(extack, + "Can't enable shared pool in switchdev mode"); + err = -EOPNOTSUPP; + goto out; + } + counts = spool_size >> PAGE_SHIFT; + enable = !(counts == 0); + esw->params.enable_shared_rx_ring = enable; + esw->params.shared_rx_ring_counts = enable ? counts : 0; + +out: + up_write(&esw->mode_lock); + return err; +} + +int mlx5_devlink_eswitch_spool_size_get(struct devlink *devlink, + u32 *spool_size) +{ + struct mlx5_eswitch *esw; + bool enable; + + esw = mlx5_devlink_eswitch_get(devlink); + if (IS_ERR(esw)) + return PTR_ERR(esw); + + enable = esw->params.enable_shared_rx_ring; + if (enable) + *spool_size = esw->params.shared_rx_ring_counts << PAGE_SHIFT; + else + *spool_size = 0; + + return 0; +} + static bool mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num) {