| Message ID | 20240402-rzn1-gmac1-v1-1-5be2b2894d8c@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: stmmac: Add support for RZN1 GMAC devices | expand |
Hi Romain, On Tue, Apr 2, 2024 at 2:36 PM Romain Gantois <romain.gantois@bootlin.com> wrote: > From: Clément Léger <clement.leger@bootlin.com> > > The RZ/N1 series of MPUs feature up to two Gigabit Ethernet controllers. > These controllers are based on Synopsys IPs. They can be connected to > RZ/N1 RGMII/RMII converters. > > Add a binding that describes these GMAC devices. > > Signed-off-by: "Clément Léger" <clement.leger@bootlin.com> > [rgantois: commit log] > Signed-off-by: Romain Gantois <romain.gantois@bootlin.com> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml > +examples: > + - | > + #include <dt-bindings/clock/r9a06g032-sysctrl.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + ethernet@44000000 { > + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; > + reg = <0x44000000 0x2000>; > + interrupt-parent = <&gic>; There is no need to use interrupt-parent in examples. > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > + clock-names = "stmmaceth"; > + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; If you want this to be a real example, you should add power-domains. > + snps,multicast-filter-bins = <256>; > + snps,perfect-filter-entries = <128>; > + tx-fifo-depth = <2048>; > + rx-fifo-depth = <4096>; > + pcs-handle = <&mii_conv1>; > + phy-mode = "mii"; > + }; Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml new file mode 100644 index 000000000000..c6f61fb1e5b0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/renesas,rzn1-gmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas GMAC + +maintainers: + - Romain Gantois <romain.gantois@bootlin.com> + +select: + properties: + compatible: + contains: + enum: + - renesas,r9a06g032-gmac + - renesas,rzn1-gmac + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-gmac + - const: renesas,rzn1-gmac + - const: snps,dwmac + + pcs-handle: + description: + phandle pointing to a PCS sub-node compatible with + renesas,rzn1-miic.yaml# + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + ethernet@44000000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44000000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clock-names = "stmmaceth"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + pcs-handle = <&mii_conv1>; + phy-mode = "mii"; + }; + +...